i.MX7ULP工业应用：双核处理器的数据手册概览

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IMX7ULPIECB2数据手册详细介绍了NXP公司的i.MX7ULP系列处理器，专为低功耗、高性能和确定性需求的应用设计。这款异构多核处理器（Heterogeneous Multicore Processing, HMP）采用双处理域架构：一个是应用处理域，基于ARM Cortex-A7内核，集成了ARM NEON SIMD引擎和浮点运算单元(FPU)，适用于运行复杂操作系统（如RTOS）的富客户端应用程序；另一个是实时处理域，由ARM Cortex-M4内核驱动，具备低功耗特性和FPU，旨在提供最低的泄漏电流。应用处理域以其强大的计算能力为核心，支持高性能处理任务，适合需要丰富功能和高效能的场景。而实时处理域则专注于可靠的时间敏感任务，如工业自动化、传感器处理等，通过独立的电源、时钟和外围设备域确保了对时间敏感操作的精确执行。这两个处理域虽然独立工作，但通过紧密集成的总线结构，实现了高效的数据交换，确保了系统的无缝协作。i.MX7ULP的精简设计减少了引脚数量，支持小型化封装和简化系统集成，从而降低了总体成本并提高了设计灵活性。此外，手册还列出了i.MX7ULP的一些关键特性，包括： 1. 应用处理器域：采用ARM Cortex-A7处理器，支持高性能计算和多媒体处理。 2. 实时处理器域：ARM Cortex-M4内核，专为实时性和低功耗优化。 3. SIMD加速：通过NEON技术提升并行处理能力。 4. FPU支持：增强了浮点运算性能，适用于需要精确计算的任务。 5. 独立控制：每个处理域都有独立的资源管理，保证了任务的有序执行。 6. 高效通信：集成总线结构利于数据传输和处理域间的协同工作。 IMX7ULPIECB2数据手册提供了全面的技术细节，为开发者在设计低功耗、高性能和可扩展的工业级应用系统时提供了强大且灵活的解决方案。通过理解和利用这些特性，工程师可以更好地构建满足特定需求的产品，并优化资源分配，以实现最佳性能与功耗平衡。

Table 1. i.MX 7ULP modules list (continued)

Block Name Block Mnemonic Subsystem Power

Domain

Brief description

PCC2 and PCC3 are in the application

domain.

Reset Mode

Controller

RMC System Control DGO Reset Mode Controller (RMC)

implements reset modes and reset

functions of the chip.

On-Chip One-Time-

Programmable

Controller

OCOTP_CTRL System Control RT The On-Chip One-Time-Programmable

Controller (OCOTP_CTRL) module

provides an interface for reading,

programming and/or overriding

identification and control information

stored in on-chip fuse elements. The

module supports electrically-

programmable poly fuses. The

OCOTP_CTRL also provides a set of

volatile software-accessible signals

which can be used for software control

of hardware elements, not requiring

non-volatility.

Peripheral Trigger

Multiplexing

TRGMUX0-1 System Control AD, RT Peripheral Trigger Multiplexing

(TRGMUX) TRGMUX0 is in the real-

time domain. TRGMUX1 is in the

application domain.

Port Control PCTL_A-F System Control AD, RT The Port Control (PCTL) module

provides control for GPIO interrupt

function. GPIO interrupt can be

configured independently for each pin in

the 32-bit port. There is one instance of

the PCTL module for each port.

PCTL_A and PCTL_B are in the real-

time domain. PCTL_C - PCTL_F are in

the application domain.

Quad Serial

Peripheral Interface

QSPI Memories and

Memory Controllers

RT The Quad Serial Peripheral Interface

(QSPI) module provides an interface to

various types of serial flash memory.

The QSPI interface allows one serial

flash connection. It supports 1-bit, 4-bit

and 8-bit SPI bus width.

Rapid General-

Purpose Input and

Output

RGPIO2P0-1 System Control AD, RT The Rapid General-Purpose Input and

Output with 2 Ports (RGPIO2P) is

similar to the RGPIO module, except it

has an AHB-lite port, in addition to the

IPS port, for faster access. RGPIO2P0

is in the real-time domain. RGPIO2P1 is

in the application domain.

Read-only memory

Controller

ROMCP0/1 Memories and

Memory Controllers

AD, RT A ROM controller and boot ROM are

present in for both the A7 and M4 CPU

cores. ROMCP0 and a 64 kB ROM are

in the real-time domain. ROMCP1 and a

96 kB ROM are in the application

domain.

Table continues on the next page...

i.MX 7ULP modules list

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

Table 1. i.MX 7ULP modules list (continued)

Block Name Block Mnemonic Subsystem Power

Domain

Brief description

Real Time Clock

Oscillator

RTC OSC Clock Sources and

Control

VBAT The Real Time Clock Oscillator (RTC

OSC) module provides the clock source

for the Real-Time Clock module. The

RTC OSC module, in conjunction with

an external crystal, generates a 32.678

kHz reference clock for the RTC.

Single Wire Output SWO Debug RT Single Wire Output (SWO) is a trace

data drain that acts as bridge between

the on-chip trace data to a data stream

that is captured by the Trace Port

Analyzer. It is a TPIU-like device that

supports a limited subset of the full

TPIU functionality for a simple debug

solution.

Secure JTAG

Controller

SJC Debug RT The Secure JTAG Controller (SJC) is an

authenticated debug module that

implements a challenge/response

mechanism using a standard

cryptographic algorithm. This allows

post production silicon debug without

compromising security requirements.

The SJC is connected in parallel with

the JTAGC module, but it is only used

for authenticated debug.

Secure Non-Volatile

Storage

SNVS Security VBAT The Secure Non-Volatile Storage

(SNVS) module is designed to safely

hold security-related data such as

cryptographic key, time counter,

monotonic counter, and general

purpose security information. A part of

the SNVS module belongs to the VBAT

domain that has its own dedicated

power supply which is always on. This

enables SNVS to keep this data valid

and continue to increment the time

counter when the power goes down in

the rest of the SoC. SNVS includes the

Real-Time Clock (RTC) module, which

provides 64-bit monotonic counter with

roll-over protection, 32-bit seconds

counter with roll-over protection and 32-

bit alarm.

Slow Internal

Reference Clock

SIRC Clock Sources and

Control

SYS The Slow Internal Reference Clock

(SIRC) module is an internal oscillator

that can generate a reference clock of

16 MHz. The SIRC output clock is used

as a reference to the SCG module, and

it is also used as a clock option to most

on-chip modules.

Table continues on the next page...

i.MX 7ULP modules list

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

Table 1. i.MX 7ULP modules list (continued)

Block Name Block Mnemonic Subsystem Power

Domain

Brief description

Synchronous Audio

Interface

SAI0-1 Multimedia RT The Synchronous Audio Interface (SAI)

module implements full-duplex serial

interfaces with frame synchronization

such as I2S, AC97, and CODEC/DSP

interfaces.

System Clock

Generation

SCG0-1 Clock Sources and

Control

AD, RT The System Clock Generation (SCG)

module is responsible for clock

generation and distribution across this

device. Functions performed by the

SCG include: clock reference selection,

generation of clock used to derive

processor, system, peripheral bus and

external memory interface clocks;

source selection for peripheral clocks;

and, control of power saving clock

gating mode. SCG0 is in the real-time

domain. SCG1 is in the application

domain.

System Integration

Module

SIM System Control AD, RT The System Integration Module (SIM)

provides system control and chip

configuration registers. The SIM

includes the TSTMR module.

System Oscillator SYS OSC Clock Sources and

Control

SYS The System Oscillator (SYS OSC)

module is a crystal oscillator. The SYS

OSC, in conjunction with an external

crystal or resonator, generates a

reference clock for this device. It also

optionally supports an external input

clock provided to EXTAL signal directly.

Tightly-Coupled

Memory

TCM Memories and

Memory Controllers

RT Tightly Coupled Memory (TCM) RAM.

This RAM is tightly integrated to the M4

processor. M4 accesses this memory

with zero wait-state. There is a

backdoor port that allows M4 DMA and

other bus masters in the SoC to access

this memory.

Timer/Pulse Width

Modulation

LPTPM0-7 Timers AD, RT The Timer/Pulse Width Modulation

Module (TPM) is a multichannel timer

module that supports input capture,

output compare, and the generation of

PWM signals. The counter, compare

and capture registers are clocked by an

asynchronous clock that can remain

enabled in low power modes. LPTPM0

– LPTPM3 are in the real-time domain.

LPTPM4 – LPTPM7 are in the

application domain.

TimeStamp

Components

TimeStamp

Components

Debug RT The timestamp components generate

and distribute a consistent timestamp

Table continues on the next page...

i.MX 7ULP modules list

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

Table 1. i.MX 7ULP modules list (continued)

Block Name Block Mnemonic Subsystem Power

Domain

Brief description

value for multiple processors and other

blocks in a SoC.

Timestamp timer TSTMR Timers AD, RT The TSTMR module is a free running

incrementing counter that starts running

after system reset de-assertion and can

be read at any time by the software for

determining the software ticks. The

TSTMR is a 64-bit clock cycle counter.

It runs off the 1 MHz clock and resets

on every system reset. The counter only

stops when the clock to the TSTMR is

disabled.

Trace Funnel FUNL Debug RT The Trace Funnel (FUNL) is used when

there is more than one trace source.

The Trace Funnel combines multiple

trace streams onto a single ATB bus.

The Trace Funnel includes an arbiter

that determines the priority of the ATB

inputs.

Trace Port Interface

Unit

TPIU Debug RT Trace Port Interface Unit (TPIU) acts as

a bridge between on-chip trace data, ID

distinguishable, and a TPA. It receives

ATB trace data and sends it off chip via

ARM’s standard trace interface. The

TPIU includes ATB interface, APB

interface, Formatter, Asynchronous

FIFO, Register bank, Trace out

serializer, and a pattern generator.

Trace Replicator Replicator Debug RT The Trace Replicator (Replicator)

enables two trace sinks (TPIU and

TMC) to be wired together and receive

ATB trace data from the same trace

source. It takes incoming data from a

single source and replicates it to two

master ports.

True Random

Number Generator

TRNG Security RT The True Random Number Generator

(TRNG) module is to generate high

quality, cryptographically secure,

random data. The TRNG module is

capable of generating its own entropy

using an integrated ring oscillator. In

addition, the module’s NIST certifiable

Pseudo-Random Number Generator

(PRNG) provides accelerated

processing of pseudo-random data.

ultra Secured Digital

Host Controller

uSDHC0/1 Memories and

Memory Controllers

AD The ultra Secured Digital Host

Controller (uSDHC) provides the

interface between the host system and

SD, SDIO or eMMC cards. The uSDHC

acts as a bridge, passing host bus

Table continues on the next page...

i.MX 7ULP modules list

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

Table 1. i.MX 7ULP modules list (continued)

Block Name Block Mnemonic Subsystem Power

Domain

Brief description

transactions to the cards by sending

commands and performing data

accesses to/from the cards or devices.

It handles SD, SDIO and eMMC

protocol at transmission level.

Universal Serial Bus

High-Speed Inter

Chip Physical Layer

HSIC-PHY Connectivity and

Communications

AD USB High-Speed Inter Chip Physical

Layer (HSIC-PHY) is a complete digital

IP designed to implement USB 2.0

HSIC connectivity interface.

Universal Serial Bus

On-The-Go

USB-OTG Connectivity and

Communications

AD The Universal System Bus On-The-Go

(USB-OTG) module is a USB 2.0-

compliant implementation. The registers

and data structures of this USB

controller are based on the Enhanced

Host Controller Interface Specification

for Universal Serial Bus (EHCI). This

module can act as a host, a device or

an On-The-Go negotiable host/device

on the USB bus.

Universal Serial Bus

Phase Locked Loop

USB PLL Clock Sources and

Control

AD USB Phase Locked Loop (USB PLL) is

embedded in the USB transceiver block.

This PLL allows an exact 480 MHz to be

generated from a supported reference

clock of 24 MHz. The output of this PLL

is primarily used for PLL operation. The

USB PLL clock is also made available

as a clock source for other peripherals

in the SoC.

Universal Serial Bus

Physical Layer

USB-PHY Connectivity and

Communications

AD The Universal System Bus Physical

Layer (USB-PHY) implements USB

physical layer connecting to USB host/

device systems at low-speed, full-

speed, and high-speed. USB-PHY

provides a standard UTMI interface for

connection to the USB-OTG controller.

Video Input Unit VIU Multimedia AD The Video Input Unit (VIU) provides a

parallel interface for digital video. The

VIU accepts various types of digital

video input on its parallel interface,

decodes it and optionally performs

processes such as down-scaling,

horizontal up-scaling, brightness and

contrast adjustment, pixel format

conversion, deinterlacing and horizontal

mirroring. The resultant video stream is

then stored to system memory for

subsequent post-processing and

display.

Wakeup Unit

WKPU System Control AD Wakeup Unit (WKPU) module is

capable of interrupt detection and wake-

Table continues on the next page...

i.MX 7ULP modules list

i.MX 7ULP Applications Processor—Industrial, Rev. 1, 07/2021

NXP Semiconductors

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