SN75DP126：DisplayPort TMDS转换器的高性能特性

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本文档介绍的是SN75DP126这款具有最小传输差分信号（TMDS）转换器，它专用于DisplayPort技术的1:2开关功能。该产品是 Texas Instruments (TI) 的一款高性能解决方案，旨在支持DisplayPort标准，包括DPv1.1a和DPv1.2信令，适用于笔记本电脑、台式计算机以及各种多媒体接口需求。 SN75DP126的特点亮点如下： 1. **双路模式支持**：作为DisplayPort++ (DP++)接口，它能够同时处理两个独立的视频路径，提供高清晰度的多媒体输出，支持最高5.4Gbps的数据速率，如HBR2模式。 2. **兼容性广泛**：这款转换器兼容DisplayPort 1.1a、1.2标准，并支持HDMI 1.4b和DVI数字视频接口，确保设备间的无缝连接。 3. **长距离传输**：支持最长10米的线缆，且TMDS时钟频率高达340MHz，满足高带宽需求。 4. **广泛的适用场景**：可用于笔记本电脑、台式计算机扩展坞、独立视频卡等，特别适合与AMD、Intel和NVIDIA等处理器的图形处理单元进行无损逻辑连接。 5. **自动链路协商**：具备自动配置功能，能够与HDMI/DVI接收端口进行链路协商，确保信号质量和稳定性。 6. **DDC通道访问**：允许通过针脚与DisplayPort端口连接的DP-HDMI适配器进行DP端口ID的访问，便于设备管理。 7. **信号调节灵活性**：支持可调电压摆幅、预加重增益等功能，以优化输出信号质量，适应不同的输入信号要求。 8. **显示数据通道管理**：为显示数据提供可调整的输入变量均衡器，确保信号的稳定传输。 SN75DP126是一款功能强大且高度灵活的DisplayPort TMDS转换器，适用于多种电子设备间的信号转换和高清多媒体传输，尤其在需要长距离和高数据速率的场景下表现出色。

SN75DP126

ZHCS794A –FEBRUARY 2012–REVISED MARCH 2012

www.ti.com.cn

PIN FUNCTIONS (continued)

I/O DESCRIPTION

SIGNAL NO.

SN75DP126SS: Digital voltage regulator decoupling; install 1uF to GND.

DD_DREG

SN75DP126DS: Treat same as V

; this pin will be most noisy of all V

terminals and needs a de-coupling

capacitor nearby.

GND Exposed Thermal Pad Ground. Reference GND connection shall be made to the exposed thermal pad.

NC 9, 53, 38, 48, 24 No connect. These terminals may be left unconnected, or connect to GND.

ORDERING INFORMATION

(1)

PART NUMBER PART MARKING PACKAGE

SN75DP126DSRHUR DP126DS 56-pin QFN Reel

SN75DP126SSRHUR DP126SS 56-pin QFN Reel

(1) For the most current package and ordering information, see Packet Option Addendum at the end of this document, or see the TI web

site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE UNIT

–0.3 to 4.0 V

Supply voltage range

, V

DD_DREG

–0.3 to 1.3 V

Main Link I/O Differential Voltage –0.3 to 1.4 V

DP_HPD_SNK, TMDS_HPD_SNK, SCL_SNK, SDA_SNK –0.3 to 5.5 V

Voltage range

EN –0.3 to 1.3 V

All Other Terminals –0.3 to 4.0 V

Human Body Model

(2)

±2 kV

Electrostatic

All Terminals

discharge

Charged-device model

(3)

±1000 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Tested in accordance with JEDEC Standard 22, Test Method A114-B

(3) Tested in accordance with JEDEC Standard 22, Test Method C101-A

THERMAL INFORMATION

THERMAL METRIC

(1)

RHU (QFN-56) UNITS

Junction-to-ambient thermal resistance 35

JCtop

Junction-to-case (top) thermal resistance 25

Junction-to-board thermal resistance 15

°C/W

Junction-to-top characterization parameter 2

Junction-to-board characterization parameter 10

JCbot

Junction-to-case (bottom) thermal resistance 8

(1) 有关传统和新的热度量的更多信息，请参阅 IC

封装热度量

应用报告 SPRA953。

SN75DP126

www.ti.com.cn

ZHCS794A –FEBRUARY 2012–REVISED MARCH 2012

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Supply voltage 3 3.3 3.6 V

Digital core and Main Link supply voltage 1.0 1.05 1.2 V

Operating free-air temperature 0 85 °C

Storage temperature -65 150 °C

CASE

Case temperature 97.1 °C

DP++ MAIN LINK TERMINALS

Peak-to-peak input differential voltage; RBR, HBR, HBR2 0.3 1.40 Vpp

R(DP)

Data rate; DisplayPort sink 5.4 Gbps

R(HDMI)

Data rate; HDMI sink 3.4 Gbps

AC coupling capacitance (each DP input and each DP output line) 75 200 nF

tdiff

Differential output termination resistance; DisplayPort sink and HDMI sink 80 100 120 Ω

Oterm

Output termination voltage (AC coupled) 0 2 V

SK(HBR2)

Intra-pair skew at the input at 5.4 Gbps 20 ps

SK(HBR)

Intra-pair skew at the input at 2.7 Gbps 100 ps

SK(RBR)

Intra-pair skew at the input at 1.62 Gbps 300 ps

AUX CHANNEL DATA TERMINALS

I-DC

DC Input Voltage, AUX_SRCp/n and AUX_SNKp/n (DP and TMDS modes) -0.5 3.6 V

Differential input voltage amplitude (DP mode only) 300 1400 mV

R(AUX)

Data rate (before Manchester encoding) 0.8 1 1.2 Mbps

R(FAUX)

Data rate Fast AUX (300ppm frequency tolerance) 720 Mbps

jccin_adj

Cycle-to-cycle AUX input jitter adjacent cycle (DP mode only) 0.05 UI

jccin

Cycle-to-cycle AUX input jitter within one cycle (DP mode only) 0.1 UI

AUX AC coupling capacitance 75 200 nF

DDC, LOCAL I

C, AND CONTROL TERMINALS

I-DC

DC Input Voltage DP_HPD_SNK, TMDS_HPD_SNK, SCL/SDA_SNK –0.3 5.5 V

All other DDC, local I

C, and control terminals –0.3 3.6

High-level input voltage SCL/SDA_SRC 2.1 V

All other DDC, Local I

C, and control terminals V

–0.5

Low-level input voltage

(1)

0.5 V

Mid-level input voltage

(2)

/2–0.3 V

/2+0.3

Data rate 100 kbps

TH(EN)

EN input threshold voltage 280 800 mV

SCL

SCL clock frequency standard I

C mode 100 kHz

w(L)

SCL clock low period standard I

C mode 4.7 μs

w(H)

SCL clock high period standard I

C mode 4.0 μs

bus

Total capacitive load for each bus line (DDC and local I

C terminals) 400 pF

(1) V

for SCL_SRC and SDA_SRC are listed in the AUX/DDC/I

C Electrical Characteristics Table.

(2) V

is only applicable for 3-Level control pins.

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SN75DP126：DisplayPort TMDS转换器的高性能特性

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