TI ADS130B02-Q1：汽车级双通道高精度ADC，满足AEC-Q100标准

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TI-ADS130B02-Q1是一款专为汽车应用设计的高性能、低功耗的2通道、32千样本/秒（kSPS）同时采样、16位Δ-Σ模数转换器（ADC）。这款设备通过AEC-Q100认证，确保在严苛的温度范围内(-40°C至+125°C)保持稳定性能，特别适合于对功能安全有严格要求的应用。该ADC的主要特点包括： 1. AEC-Q100兼容性：针对汽车行业严格的温度和电磁兼容性标准，满足AEC-Q100等级1的要求，确保在宽温范围内的可靠运行。 2. 功能安全：提供相关的文档支持，帮助设计者实现安全系统，提高系统的可靠性和稳定性。 3. 双通道同步采样：允许同时对两个差分输入信号进行高效处理，便于多通道信号采集和分析。 4. 可编程数据速率：最高可达32千样本/秒，根据应用需求灵活调整。 5. 可编程增益：最大增益为128，适应不同范围的信号输入。 6. 全局切片模式：通过消除温度和时间变化带来的漂移，确保长期稳定性和精度。 7. 高阻抗模拟输入接口：方便直接连接传感器，减少外部负载的影响。 8. 内置负向充电泵：支持测量低于地电位的输入信号，扩展了输入信号范围。 9. 极低的通道间干扰：高达-120分贝的交叉 talk抑制，减小噪声影响。 10. 低漂移内部参考电压：1.2伏的高精度内参考源，保证测量的准确性。 11. 精密内部振荡器：提供稳定的时钟源，确保采样精确。 12. 通信与寄存器映射：CRCon通信接口和清晰的寄存器地图设计，简化系统集成和配置。 13. 电源需求：工作电压范围宽，2.7V至3.6V的模拟和数字供电，而在3.3伏AVDD和DVDD下，功耗仅为3毫瓦。 14. 广泛应用领域： - 电动汽车充电站：用于直流电能计量。 - 汽车电池管理系统（BMS）：进行电流、电压和温度测量，如利用外部电阻分压器进行电压测量，或通过热敏电阻测量电池温度。综合以上特性，TI-ADS130B02-Q1是汽车电子系统中一个关键的信号转换元件，它能够准确、快速地处理各种信号，并在恶劣环境中保持良好的性能表现，为汽车行业的许多关键应用提供了理想的解决方案。

6.9 Typical Characteristics (continued)

at T

= 25°C, AVDD = 3.3 V, DVDD = 3.3 V, f

CLKIN

= 8.192 MHz, data rate = 4 kSPS, and gain = 1 (unless otherwise noted)

Temperature (°C)

Oscillator Frequency Error (%)

-40 -20 0 20 40 60 80 100 120 140

-3

-2

-1

Figure 6-10. Oscillator Frequency Error vs Temperature

Temperature (°C)

Analog Supply Current (mA)

-40 -20 0 20 40 60 80 100 120 140

HR Mode

LP Mode

VLP Mode

Gain = 1, OSR = 1024, all two ADC channels enabled

Figure 6-11. Analog Supply Current vs Temperature

Temperature (°C)

Analog Supply Current (mA)

-40 -20 0 20 40 60 80 100 120 140

HR Mode

LP Mode

VLP Mode

Gain = 8, OSR = 1024, all two ADC channels enabled

Figure 6-12. Analog Supply Current vs Temperature

Temperature (°C)

Digital Supply Current (mA)

-40 -20 0 20 40 60 80 100 120 140

0.1

0.2

0.3

0.4

0.5

0.6

HR Mode

LP Mode

VLP Mode

OSR = 1024

Figure 6-13. Digital Supply Current vs Temperature

Temperature (°C)

Supply Current (PA)

-40 -20 0 20 40 60 80 100 120 140

AVDD

DVDD

Standby mode

Figure 6-14. Supply Current vs Temperature

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7 Parameter Measurement Information

7.1 Noise Measurements

Adjust the data rate and gain to optimize the ADS130B02-Q1 noise performance. When averaging is increased

by reducing the data rate, noise drops correspondingly. Table 7-1 summarizes the ADS130B02-Q1 noise

performance using the 1.2-V internal reference and a 3.3-V analog power supply. The data are representative of

typical noise performance at T

= 25°C when f

MCLK

= 8.192 MHz. The modulator clock frequency f

MOD

= f

MCLK

2. The data shown are typical input-referred noise results with the analog inputs shorted together and taking

an average of multiple readings across all channels. A minimum 1 second of consecutive readings are used to

calculate the RMS noise for each reading. Table 7-2 shows the effective resolution calculated from the noise

data. Equation 1 calculates effective resolution. In each case, V

REF

corresponds to the internal 1.2-V reference.

In global-chop mode, noise is improved by a factor of √2.

The noise performance scales with the oversampling rate (OSR) and gain settings, but is independent from the

configured power mode. Thus, the device exhibits the same noise performance in different power modes when

selecting the same OSR and gain settings. However, the data rate at the OSR settings scales based on the main

clock frequency for the different power modes.

REF

RMS

2 V

Effective Resolution = log

Gain V

§ ·

¨ ¸

(1)

Table 7-1. Noise (μV

RMS

) at T

= 25°C

OSR

DATA RATE (kSPS),

MCLK

= 8.192 MHz

GAIN

1 2 4 8 16 32 64 128

16384 0.25 36.62 18.31 9.16 4.58 2.29 1.14 0.57 0.42

8192 0.5 36.62 18.31 9.16 4.58 2.29 1.14 0.57 0.58

4096 1 36.62 18.31 9.16 4.58 2.29 1.14 0.80 0.80

2048 2 36.62 18.31 9.16 4.58 2.29 1.14 1.05 1.05

1024 4 36.62 18.31 9.16 4.58 2.29 1.27 1.27 1.27

512 8 36.62 18.31 9.16 4.58 2.29 1.80 1.80 1.80

256 16 36.62 18.31 9.16 4.58 2.56 2.53 2.53 2.53

128 32 36.62 18.31 13.64 4.58 3.73 3.63 3.63 3.63

Table 7-2. Effective Resolution at T

= 25°C

OSR

DATA RATE (kSPS),

MCLK

= 8.192 MHz

GAIN

1 2 4 8 16 32 64 128

16384 0.25 16 16 16 16 16 16 16 15.4

8192 0.5 16 16 16 16 16 16 16 15.0

4096 1 16 16 16 16 16 16 15.5 14.5

2048 2 16 16 16 16 16 16 15.1 14.1

1024 4 16 16 16 16 16 15.8 14.8 13.8

512 8 16 16 16 16 16 15.3 14.3 13.3

256 16 16 16 16 16 15.8 14.9 13.9 12.9

128 32 16 16 15.4 16 15.3 14.3 13.3 12.3

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8 Detailed Description

8.1 Overview

The ADS130B02-Q1 is a low-power, two-channel, simultaneous-sampling, 16-bit, delta-sigma (ΔΣ) analog-to-

digital converter (ADC) with a low-drift internal reference voltage. The dynamic range, size, feature set, and

power consumption are optimized for cost-sensitive applications requiring simultaneous sampling.

The ADS130B02-Q1 requires both analog and digital supplies. The analog power supply (AVDD – AGND) can

operate between 2.7 V and 3.6 V. An integrated negative charge pump allows absolute input voltages as low

as 0.3 V below AGND, which enables measurements of input signals varying around ground with a unipolar

power supply. The digital power supply (DVDD – DGND) can operate between 2.7 V and 3.6 V. The device

features a high input impedance programmable gain amplifier (PGA) with gains up to 128. The ADC receives its

reference voltage from an integrated 1.2-V reference. The device allows differential input voltages as large as

the reference. Three power-scaling modes allow designers to trade power consumption for noise performance.

Each channel on the ADS130B02-Q1 contains a digital decimation filter that demodulates the output of the

ΔΣ modulators. The filter enables data rates as high as 32 kSPS per channel in high-resolution mode. The

Functional Block Diagram provides a detailed diagram of the ADS130B02-Q1.

The device communicates via a serial peripheral interface (SPI)-compatible interface. Several SPI commands

and internal registers control the operation of the ADS130B02-Q1. Other devices can be added to the same

SPI bus by adding discrete CS control lines. The SYNC/RESET pin can be used to synchronize conversions

between multiple ADS130B02-Q1 devices as well as to maintain synchronization with external events.

8.2 Functional Block Diagram

ADC

SCLK

DOUT

DIN

AVDD

AGND

DVDD

DGND

DRDY

Oscillator

CLKIN

1.2-V

Reference

SYNC/RESET

Digital Filter

ADC

Digital Filter

AIN0P

AIN0N

–

AIN1P

AIN1N

–

Control &

Serial Interface

Clock

Selection

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