"DS92LV0421/22: LVDS串行器与高速序列链接接口技术详解"

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TI-DS92LV0421.pdf is a datasheet for the LVDS serializer, DS92LV0421 and DS92LV0422 high-speed serial link devices. These devices are designed for use in RGB style display interfaces, frame grabbers, RGB displays, and other similar applications. They support resolutions ranging from QVGA to XGA with a 24-bit color depth, making them ideal for high-performance display systems. The DS92LV0421 and DS92LV0422 feature a Channel Link II interface, which includes Channel Link, CMF, and RxIN1/-RxCLKIN/-RxIN2/-RxIN0/-RxIN3/-TxOUT1/-TxCLKOUT/-TxOUT2/-TxOUT0/-TxOUT3/-3.3V connections. These devices support multiple configuration modes, including MAPSEL, SSC, VODSEL, CONFIG[1:0], BISTEN, OSELL, and FMODE. They also have built-in de-emphasis and BIST (Built-In Self-Test) functionality for enhanced performance and reliability. The DS92LV0421 and DS92LV0422 devices operate at a low voltage of 1.8V or 3.3V, making them suitable for a wide range of applications. They can be easily integrated into existing systems and are compatible with standard STP cables. Additionally, these devices support SDAID[x] and SCL Optional interfaces for connection to cameras or AFEs (Analog Front Ends). Overall, the TI-DS92LV0421.pdf datasheet provides comprehensive information on the features and specifications of the DS92LV0421 and DS92LV0422 devices, making them an excellent choice for designers looking to implement high-speed serial links in their display systems. With their advanced functionality and compatibility with various display interfaces, these devices offer a versatile solution for a wide range of applications in the field of digital displays and image processing.

DS92LV0421

DS92LV0422

SNLS325D –MAY 2010–REVISED DECEMBER 2016

www.ti.com

Product Folder Links: DS92LV0421 DS92LV0422

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Based on nine thermal vias.

6.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)

THERMAL METRIC

(1)

DS92LV0421 DS92LV0422

UNITNJK (WQFN) RHS (WQFN)

36 PINS 48 PINS

θJA

Junction-to-ambient thermal resistance

(2)

33.8 28.8 °C/W

θJC(top)

Junction-to-case (top) thermal resistance

(2)

15.8 9.3 °C/W

θJB

Junction-to-board thermal resistance 7.2 5.7 °C/W

Junction-to-top characterization parameter 0.2 0.1 °C/W

Junction-to-board characterization parameter 7.1 5.7 °C/W

θJC(bot)

Junction-to-case (bottom) thermal resistance 2.6 1.6 °C/W

(1) Typical values represent most likely parametric norms at V

= 3.3 V, T

= +25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not verified.

(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V

, ΔV

, V

, and V

, which are differential voltages.

6.5 Electrical Characteristics: Serializer DC

over recommended operating supply and temperature ranges (unless otherwise noted)

(1)(2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LVCMOS INPUT DC SPECIFICATIONS

High-level input voltage

DDIO

= 3 V to 3.6 V (PDB, VODSEL, MAPSEL,

CONFIG[1:0], BISTEN pins)

2 V

DDIO

= 1.71 V to 1.89 V (PDB, VODSEL, MAPSEL,

CONFIG[1:0], BISTEN pins)

0.65 ×

DDIO

Low-level input voltage

DDIO

= 3 V to 3.6 V (PDB, VODSEL, MAPSEL,

CONFIG[1:0], BISTEN pins)

GND 0.8

DDIO

= 1.71 V to 1.89 V (PDB, VODSEL, MAPSEL,

CONFIG[1:0], BISTEN pins)

GND

0.35 ×

DDIO

Input current

= 0 V or V

DDIO

(PDB,

VODSEL, MAPSEL,

CONFIG[1:0], BISTEN pins)

DDIO

= 3 V to 3.6 V −15 ±1 15

µA

DDIO

= 1.7 V to

1.89 V

−15 ±1 15

CHANNEL LINK PARALLEL LVDS RECEIVER DC SPECIFICATIONS

Differential threshold, high

voltage

= 1.2 V (see Figure 1),

RXIN[3:0]± and RXCLKIN± pins

100 mV

Differential threshold, low

voltage

= 1.2 V (see Figure 1),

RXIN[3:0]± and RXCLKIN± pins

−100 mV

Differential input voltage

swing

= 1.2 V (see Figure 1),

RXIN[3:0]± and RXCLKIN± pins

200 600 mV

Common-mode voltage

DDIO

= 3.3 V (RXIN[3:0]± and RXCLKIN± pins) 0 1.2 2.4

DDIO

= 1.8 V (RXIN[3:0]± and RXCLKIN± pins) 0 1.2 1.7

Input current RXIN[3:0]± and RXCLKIN± pins −15 ±1 15 µA

CHANNEL LINK II SERIAL CML DRIVER DC SPECIFICATIONS

Differential output voltage

= 100 Ω,

de-emphasis = disabled

(see Figure 3), DOUT+ and

DOUT– pins

VODSEL = L ±225 ±300 ±375

VODSEL = H ±350 ±450 ±550

VOD

p-p

Differential output voltage

(DOUT+) – (DOUT–)

= 100 Ω,

de-emphasis = disabled

(see Figure 3), DOUT+ and

DOUT– pins

VODSEL = L 600

mVp-p

VODSEL = H 900

ΔV

Output voltage unbalance

= 100 Ω, de-emphasis = disabled, VODSEL = L

(DOUT+ and DOUT– pins)

1 50 mV

DS92LV0421

DS92LV0422

www.ti.com

SNLS325D –MAY 2010–REVISED DECEMBER 2016

Product Folder Links: DS92LV0421 DS92LV0422

Electrical Characteristics: Serializer DC (continued)

over recommended operating supply and temperature ranges (unless otherwise noted)

(1)(2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Offset voltage

(single-ended)

At TP A and B (see Figure 2),

= 100 Ω, de-emphasis =

disabled (DOUT+ and DOUT–

pins)

VODSEL = L 1.65

VODSEL = H 1.575

ΔV

Offset voltage unbalance

(single-ended)

At TP A and B (see Figure 2), R

= 100 Ω,

de-emphasis = disabled (DOUT+ and DOUT– pins)

1 mV

Output short-circuit current

DOUT± = 0 V, de-emphasis = disabled,

VODSEL = 0 (DOUT+ and DOUT– pins)

−36 mA

Internal output termination

resistor

DOUT+ and DOUT– pins 80 120 Ω

SERIALIZER SUPPLY CURRENT

DDT1

Serializer supply current

(includes load current)

= 100 Ω, f = 75 MHz, checker board pattern (see

Figure 15), de-emphasis = 3 kΩ, VODSEL = H,

= 1.89 V (All V

pins)

84 100 mA

DDIOT1

Serializer supply current

(includes load current)

= 100 Ω, f = 75 MHz

de-emphasis = 3 kΩ,

VODSEL = H,

checker board pattern (see

Figure 15)

DDIO

= 1.89 V

DDIO

pin)

3 5

DDIO

= 3.6 V

DDIO

pin)

10 13

DDT2

Serializer supply current

(includes load current)

= 100 Ω, f = 75 MHz, checker board pattern (see

Figure 15), de-emphasis = 6 kΩ, VODSEL = L,

= 1.89 V (All V

pins)

77 90 mA

DDIOT2

Serializer supply current

(includes load current)

= 100 Ω, f = 75 MHz

de-emphasis = 6 kΩ,

VODSEL = L,

checker board pattern (see

Figure 15)

DDIO

= 1.89 V

DDIO

pin)

3 5

DDIO

= 3.6 V

DDIO

pin)

10 13

DDZ

Serializer supply current

power-down

PDB = 0 V, all other LVCMOS inputs = 0 V,

= 1.89 V (All V

pins)

100 1000 µA

DDIOZ

Serializer supply current

power-down

PDB = 0 V, all other LVCMOS

inputs = 0 V

DDIO

= 1.89 V

DDIO

pin)

0.5 10

µA

DDIO

= 3.6 V

DDIO

pin)

1 30

(1) Typical values represent most likely parametric norms at V

= 3.3 V, T

= +25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not verified.

(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except V

, ΔV

, V

, and V

, which are differential voltages.

6.6 Electrical Characteristics: Deserializer DC

over recommended operating supply and temperature ranges (unless otherwise noted)

(1)(2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

3.3-V LVCMOS I/O DC SPECIFICATIONS (V

DDIO

= 3 V to 3.6 V)

High level input voltage

PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],

and BISTEN pins

2 V

DDIO

Low level input voltage

PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],

and BISTEN pins

GND 0.8 V

Input current

= 0 V or V

DDIO

(PDB, VODSEL, OEN, MAPSEL,

LFMODE, SSC[2:0], and BISTEN pins)

−15 ±1 15 µA

High level output voltage I

= –0.5 mA (LOCK and PASS pins)

DDIO

–

0.2

DDIO

Low level output voltage I

= 0.5 mA (LOCK and PASS pins) GND 0.2 V

Output short-circuit current V

OUT

= 0 V (LOCK and PASS pins) –10 mA

TRI-STATE output current

PDB = 0 V, OSS_SEL = 0 V, V

OUT

= 0 V or V

DDIO

(LOCK and PASS pins)

–10 10 µA

DS92LV0421

DS92LV0422

SNLS325D –MAY 2010–REVISED DECEMBER 2016

www.ti.com

Product Folder Links: DS92LV0421 DS92LV0422

Electrical Characteristics: Deserializer DC (continued)

over recommended operating supply and temperature ranges (unless otherwise noted)

(1)(2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

1.8-V LVCMOS I/O DC SPECIFICATIONS (V

DDIO

= 1.71 V to 1.89 V)

High level input voltage

PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],

and BISTEN pins

0.65 ×

DDIO

Low level input voltage

PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0],

and BISTEN pins

GND

0.35 ×

DDIO

Input current

= 0 V or V

DDIO

(PDB, VODSEL, OEN, MAPSEL,

LFMODE, SSC[2:0], and BISTEN pins)

−15 ±1 15 µA

High level output voltage I

= –0.5 mA (LOCK and PASS pins)

DDIO

–

0.2

DDIO

Low level output voltage I

= 0.5 mA (LOCK and PASS pins) GND 0.2 V

Output short-circuit current V

OUT

= 0 V (LOCK and PASS pins) –3 mA

TRI-STATE output current

PDB = 0 V, OSS_SEL = 0 V, V

OUT

= 0 V or V

DDIO

(LOCK and PASS pins)

–15 15 µA

CHANNEL LINK PARALLEL LVDS DRIVER DC SPECIFICATIONS

| Differential output voltage

= 100 Ω

(see Figure 3; TXOUT[3:0]± and

TXCLKOUT± pins)

VODSEL = L 100 250 400

VODSEL = H 200 400 600

ODp-p

Differential output voltage

A to B

= 100 Ω

(see Figure 3; TXOUT[3:0]± and

TXCLKOUT± pins)

VODSEL = L 500

mVp-p

VODSEL = H 800

ΔV

Output voltage unbalance

= 100 Ω

(see Figure 3; TXOUT[3:0]± and TXCLKOUT± pins)

1 50 mV

Offset voltage

(single-ended)

= 100 Ω

(see Figure 3; TXOUT[3:0]± and

TXCLKOUT± pins)

VODSEL = L 1 1.2 1.5

VODSEL = H 1.2

ΔV

Offset voltage unbalance

(single-ended)

= 100 Ω (see Figure 3; TXOUT[3:0]± and

TXCLKOUT± pins)

1 50 mV

Output short-circuit current

= 100 Ω, V

OUT

= GND

(TXOUT[3:0]± and TXCLKOUT± pins)

–5 mA

Output TRI-STATE current

= 100 Ω, V

OUT

= V

DDTX

or GND

(TXOUT[3:0]± and TXCLKOUT± pins)

–10 10 µA

CHANNEL LINK II SERIAL CML RECEIVER DC SPECIFICATIONS

Differential input threshold

high voltage

= 1.2 V (Internal V

BIAS

)

(RIN+ and RIN- pins)

50 mV

Differential input threshold

low voltage

= 1.2 V (Internal V

BIAS

)

(RIN+ and RIN- pins)

–50 mV

Common mode voltage,

internal V

BIAS

RIN+ and RIN- pins 1.2 V

Input termination RIN+ and RIN- pins 85 100 115 Ω

DESERIALIZER SUPPLY CURRENT

DD1

Deserializer supply current

(Includes load current)

75 MHz clock, checker board pattern (see

Figure 15), VODSEL = H, SSCG[2:0] = 000'b,

DDn

= 1.89 V (All V

DD(1.8)

pins)

88 100 mA

DDTX1

Deserializer supply current

(Includes load current)

75 MHz clock, checker board pattern (see

Figure 15), VODSEL = H, SSCG[2:0] = 000'b,

DDTX

= 3.6 V (V

DDTX

pin)

40 50 mA

DDIO1

Deserializer supply current

(Includes load current)

75 MHz clock,

checker board pattern (see

Figure 15), VODSEL = H,

SSCG[2:0] = 000'b

DDIO

= 1.89 V

DDIO

pin)

0.3 0.8

DDIO

= 3.6 V

DDIO

pin)

0.8 1.5

DDZ

Deserializer supply current

power-down

PDB = 0 V, All other LVCMOS inputs = 0 V,

DDn

= 1.89 V (All V

DD(1.8)

pins)

0.15 2 mA

DDTXZ

Deserializer supply current

power-down

PDB = 0 V, All other LVCMOS inputs = 0 V,

DDTX

= 3.6 V (V

DDTX

pin)

0.01 0.1 mA

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