"SDIO4.0协议英文原版学习指南"

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The SDIO 4.0 protocol, released in February 2012, is a comprehensive document detailing the specifications for SDIO (Secure Digital Input Output) devices. This English version of the SDIO 4.0 protocol serves as a valuable resource for individuals seeking to understand the intricacies of the SDIO protocol. Developed by the Technical Committee of the SD Card Association, the SDIO 4.0 protocol outlines the standards and guidelines for the interaction between SDIO devices and host systems. Realtek Semiconductor Corp. played a significant role in the development and dissemination of this protocol, as evidenced by the fact that Ally Chiang of Realtek Semiconductor Corp. downloaded the document in March 2012. The SDIO 4.0 protocol, which supersedes previous versions, features enhancements and updates that improve the functionality and performance of SDIO devices. The protocol outlines the communication protocols, data transfer rates, power management, and security measures that SDIO devices must adhere to for seamless operation. This document, protected by copyright from 2000 to 2012, is a valuable asset for manufacturers, developers, and researchers working in the field of SDIO technology. By studying the SDIO 4.0 protocol, individuals can gain a deeper understanding of the intricacies of SDIO devices and ensure compliance with industry standards. In conclusion, the SDIO 4.0 protocol is a crucial document for anyone involved in the design, development, and implementation of SDIO devices. Its detailed specifications and guidelines provide a roadmap for the successful integration of SDIO technology into various applications and systems. As technology continues to advance, the SDIO 4.0 protocol will serve as a pivotal resource for driving innovation and progress in the field of SDIO technology.

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SDIO Specification Version 4.00

3 Confidential

1.3 Document Structure

Reference documents are described in the Appendix A.

SDIO Specification describes modifications of the Physical Layer Specification and UHS-II Addendum,

and defines new functions for SDIO. The standard card form factors are defined in the Part 1 Mechanical

Addenda. The extended card form factors for Standard-Size SDIO card are defined in the SDIO

Specification.

This specification refers any released versions of the Physical Layer Specification Version 4.00 and later,

the UHS-II Addendum Version 1.00 and later, and the eSD Addendum Version 2.10 and later.

1.4 Standard SDIO Functions

Figure 1-1 shows the SDIO related specifications. The 4-bit SD Bus Interface and SPI Bus Interface are

defined by the Physical Layer specification and this SDIO specification, and UHS-II Bus Interface is

defined by the UHS-II Addendum. The Memory portion of a Combo card is specified by the Physical Layer

specification. An SDIO and a Combo Card have an SDIO function on the backend.

Associated with the base SDIO specification, there are several Application Specifications for Standard

SDIO Functions. The feature of SDIO is determined by a SDIO function. Card driver and application

software are required to control the function. There are two SDIO function types: standard SDIO function

and non standard SDIO function.

The standard functions such as cameras, Bluetooth cards and GPS receivers have a standard register

interface, a common operation method and a standard CIS extension. By defining a standard register

interface for a specific function, an OS vendor can provide a standard card driver, application software

and API for the functions. Full information on the standard functions is defined by Part E2 to Part E7 (Part

E7 is assigned for iSDIO (Intelligent SDIO) Specification).

In the case of non standard SDIO functions, a card or device manufacturer needs to provide a card driver.

The user may need to install the card driver and the application software to use the non standard SDIO

function. Implementation of the non standard register interfaces is optional for any card vendor, but

compliance with the standard allows the use of standard drivers and applications.

Figure 1-1 : SDIO Related Specifications

In the following Chapters and Sections, the term "card" needs to be interpreted as not only "SDIO Card

and Combo Card" but also "Embedded SDIO Device" unless otherwise noted.

Part2 File System Specification

Part3 Security Specification

CMD52, 53

PartE7 iSDIO Specification

PartE7

Wireless

LAN

Addendum

Application

PartE2

SDIO

Bluetooth

Type-A

PartE3

SDIO

Bluetooth

Type-B

PartE4

SDIO

GPS

PartE5

SDIO

Camera

PartE6

SDIO

PHS

PartE1 SDIO Specification

iSDIO Common

Interface

iSDIO

Application

Part1 Physical Layer Specification

CMD48, 49

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SDIO Specification Version 4.00

4 Confidential

2. SDIO Signaling Definition

2.1 SDIO Card Types

There are three SDIO Card types

(1) Non UHS Card

The Full-Speed Card supports SPI, 1-bit SD and the 4-bit SD interface and shall support Default

Speed mode at the clock range of 0-25MHz (up to 12.5MB/s). High-Speed mode is optional at the

clock range of 0-50MHz (up to 25MB/s).

Low-Speed SDIO Card requires only the SPI and 1-bit SD interface modes. 4-bit support is optional.

In addition, Low-Speed SDIO cards shall support clock range of 0-400 KHz.

(2) UHS-I SDIO Card

In addition to the Full-Speed Card feature, 1.8V signaling mode is supported. Support of High-Speed

mode, SDR12 (up to 12.5MB/s), SDR25 (up to 25MB/s) and SDR50 (up to 50MB/s) is mandatory and

the support of the other UHS-I modes is optional.

(3) UHS-II SDIO Card

In addition to the UHS-I SDIO Card feature, support of UHS-II mode is mandatory.

There are also Multi-Function SDIO Card and Combo Card as derivative types.

2.2 SDIO Card Modes

There are four bus modes defined for SD memory cards that also apply to SDIO Cards:

2.2.1 SPI Mode (Card mandatory support)

The SPI bus topology is defined in Section 3.5.2 and the protocol is defined in Sections 3.6.2 and Chapter

7 of the Physical Layer Specification Version 3.0x. In this mode pin 8, which is undefined for memory, is

used as the interrupt pin. All other pins and signaling protocols are identical to the Physical Layer

Specification.

New functions defined after the SDIO Version 2.00 may not be supported in the SPI mode.

2.2.2 1-bit SD Data Transfer Mode (Card Mandatory Support)

This mode is identical to the 1 data bit (narrow) mode defined for SD Memory in Section 3.6.1 of the

Physical Layer Specification. In this mode, data is transferred on the DAT[0] pin only. In this mode pin 8,

which is undefined for memory, is used as the interrupt pin and pin 9, which is undefined for memory, is

used as the read wait pin. All other pins and signaling protocols are identical to the Physical Layer

Specification.

2.2.3 4-bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional for

Low-Speed)

This mode is identical to the 4 data bit mode (wide) defined for SD Memory in Section 3.6.1 of the Physical

Layer Specification. In this mode, data is transferred on all 4 data pins (DAT[3:0]). In this mode the

interrupt pin is not available for exclusive use as it is utilized as a data transfer line. Thus, if the interrupt

function is required, special timing is required to provide interrupts. Refer to Section 8.1.2 for details of this

operation. UHS-I bus speed mode has been added from SDIO Version 3.00 onward. The 4-bit SD mode

provides the highest data transfer possible, up to 104 MB/sec.

Hereafter, 1-bit SD data transfer mode and 4-bit SD data transfer mode may be collectively called as "SD

mode".

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SDIO Specification Version 4.00

6 Confidential

It is recommended that multi-slot hosts intending to support SDIO (SDIO aware) provide a separate CLK

to each slot, to allow the I/O cards to be placed in a low power state on a slot-by-slot basis. After reset, all

data lines (DAT[3:0]) shall be in the hi-Z state on both the host and card(s) to avoid bus conflict. Access to

the Bus Interface Control register within the CCCR (Table 6-1) determines DAT line mode.

Interface for the Embedded SDIO is described in Chapter 17.

2.4.2 Signal Pins for UHS-II Interface SDIO Card

UHS-II Interface is assigned to pads on the second row.

SD Memory Card

1 2 3 4 5 6 7 8

10 1112 13 14 1516 17

SD Memory Card

1 2 3 4 5 6 7 8

10 1112 13 14 1516 17

Figure 2-2 : UHS-II Card Shape and Interface (Top View)

Figure 2-2 shows the shape of Standard Size and interface contacts of the UHS-II SD Memory Card. The

detailed physical dimensions and mechanical description are given in Part 1 Mechanical Addenda.

Table 2-2 defines the contacts for UHS-II. SD bus contacts 7 and 8 Pins are used for RCLK. The first row

contacts in non UHS-II mode are equivalent to Table 2-1. Regarding PHY I/O Type, refer to the UHS-II

Addendum for more details.

Pin # Name Type Description

4 VDD1 Supply voltage 2.7V to 3.6V

7 RCLK+ Differential Signaling: Input Clock Input

8 RCLK- Differential Signaling: Input Clock Input

9 IRQ Interrupt Output 3.3V Signal Level

10 VSS3 Ground

11 D0+ Differential Signaling: Input (FD) / Bidirectional (HD) Input in default

12 D0- Differential Signaling: Input (FD) / Bidirectional (HD) Input in default

13 VSS4 Ground

14 VDD2 Supply Voltage 2 1.70V to 1.95V

15 D1- Differential Signaling: Output (FD) / Bidirectional (HD) Output in default

16 D1+ Differential Signaling: Output (FD) / Bidirectional (HD) Output in default

17 VSS5 Ground

Table 2-2 : UHS-II Interface Pad Assignment

UHS-II Card shall not drive unused lines of SD I/F in UHS-II mode (CLK, CMD and DAT[3]). Host shall not

leave these unused lines floating, but keep them at a defined high or low level. How to keep line level is

dependent on host implementation.

2.5 Host Requirements for SDIO

2.5.1 SD Bus Interface

In order for a host to completely support all of the capabilities of the SDIO cards, some signal connections

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