LMK04610：超低噪声低功耗时钟抖动消除器

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"TI-LMK04610.pdf" LMK04610是一款高性能的时钟抖动消除器，由德州仪器（Texas Instruments，TI）制造。该器件具有双环路锁相环（PLL）架构，特别适用于需要高精度和低噪声时钟信号的系统。它符合JESD204B标准，这是一种高速串行接口标准，用于连接数字信号处理器（DSPs）、模拟前端（AFE）和类似的高速数据转换器。 LMK04610的主要特点包括： 1. **双环路PLL架构**：这种设计提高了时钟稳定性和精度，能够处理不同频率的输入和输出时钟信号。 2. **超低噪声性能**：在10kHz至20MHz的频率范围内，LMK04610表现出极低的RMS抖动，具体表现为1966.08MHz时48fs，983.04MHz时50fs，以及122.88MHz时61fs。 3. **低功耗**：设计考虑了能效，降低了运行时的功率消耗，有利于能源效率高的应用。 4. **JESD204B兼容性**：支持JESD204B标准的一次性、脉冲和连续SYSREF模式，确保与现代高速数据转换器的兼容性。 5. **10个差动输出时钟**：提供8个频率组的输出，频率范围广泛，最高可达2GHz，每个输出对可以配置为SYSREF时钟输出。 6. **可编程输出摆幅**：输出电压幅度可以在700mVpp到1600mVpp之间调整，以适应不同的系统需求。 7. **通道分频器**：内置16位通道分频器，允许灵活的时钟分频配置。 8. **最小SYSREF频率**：支持最低25kHz的SYSREF频率，确保了系统的灵活性。 9. **数字延迟**：具有精密的数字延迟功能，可以动态调整，这在需要精确时序控制的应用中非常有用。 10. **DDLY功能**：数字延迟（DDLY）可以设置为时钟周期的一半，提供了更精细的时序控制。 LMK04610是为需要高精度、低抖动时钟源的系统设计的，例如在通信、数据中心、测试测量和高性能计算等领域。它通过其强大的功能集，能够满足各种复杂的时钟同步和管理需求。为了确保最佳性能，设计者应参考最新的英文版数据表，以获取最新的技术规格和设计指导。

LMK04610

ZHCSG17B –JANUARY 2017–REVISED JULY 2019

www.ti.com.cn

(1) See applications section Power Supply Recommendations for Icc for specific part configuration and how to calculate Icc for a specific

design.

7.16 Power Supply Characteristics

3.135 V < VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE < 3.465 V;

1.7 V < VDD_IO, VDD_OSC, VDDO_x < 3.465 V; –40°C < T

< 85°C and T

PCB

≤ 105°C. Typical values at VDD_PLL2OSC,

VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC, VDDOx = 1.8 V, T

= 25°C, at the Recommended

Operating Conditions and are not assured.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DD_PD

Power-down supply current 12 20 mA

Total

Total power consumption

(1)

10 HSDS 8-mA clocks enabled at 122.88

MHz

OSCout disabled, LOS disabled

PLL1 and PLL2 locked.

122.88 MHz at CLKin0 and 122.88-MHz

VCXO

950 1050 mW

10 HSDS 4-mA clocks enabled at 122.88

MHz

OSCout disabled, LOS disabled

PLL1 and PLL2 locked.

122.88 MHz at CLKin0 and 122.88-MHz

VCXO

880 950 mW

DDO_X

CLKoutX supply current

(VDDO_3/4, VDDO_7/8)

See P

Total

Test Condition (HSDS 8-mA) 41.1 49.1 mA

DDIO

IO supply current See P

Total

Test Condition (HSDS 8-mA) 5.3 8.4 mA

DD_PLL1

PLL1 supply current See P

Total

Test Condition (HSDS 8-mA) 14.8 16.1 mA

DD_PLL2CORE

PLL2 core supply current See P

Total

Test Condition (HSDS 8-mA) 45.5 52.0 mA

DD_PLL2OSC

PLL2 OSC supply current See P

Total

Test Condition (HSDS 8-mA) 60.7 64.9 mA

DD_CORE

Core supply current See P

Total

Test Condition (HSDS 8-mA) 22.5 28.6 mA

DD_OSC

OSC supply current See P

Total

Test Condition (HSDS 8-mA) 3.2 4.1 mA

7.17 Typical Power Supply Noise Rejection Characteristics

Typical values at VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE = 3.3 V, VDD_IO, VDD_OSC,

VDDOx = 1.8 V, T

= 25°C, at the Recommended Operating Conditions and are not assured. Sinusoidal noise injected in

either of the following supply nodes: VDD_PLL2OSC, VDD_PLL1, VDD_PLL2CORE, VDD_CORE, VDD_IO, VDD_OSC, or

VDDOx

PARAMETER

TEST

CONDITION

VDD_PLL1

VDD_PLL2

OSC

VDD_PLL2

CORE

VDD_CORE

VDD_OSC/

VDD_IO

VDDOx UNIT

PSNR

10kHz

10-kHz spur on 122.88-

MHz output

25-mV ripple on

supply.

Single HSDS 8-

output enabled.

–59 –94 n/a –104 –108 n/a

dBc

PSNR

100kHz

100-kHz spur on 122.88-

MHz output

–71 –87 –101 n/a n/a –101

dBc

PSNR

500kHz

500-kHz spur on 122.88-

MHz output

–87 –81 –90 n/a n/a –93

dBc

PSNR

1MHz

1-MHz spur on 122.88-

MHz output

–100 –80 –83 n/a n/a –88

dBc

PSNR

10kHz

10-kHz spur on 122.88-

MHz output

50-mV ripple on

supply.

Single HSDS 8-

mA output

enabled.

–53 –88 –109 –100 –104 –107

dBc

PSNR

100kHz

100-kHz spur on 122.88-

MHz output

–65 –81 –98 n/a n/a –98

dBc

PSNR

500kHz

500-kHz spur on 122.88-

MHz output

–81 –75 –84 –108 n/a –87

dBc

PSNR

1MHz

1-MHz spur on 122.88-

MHz output

–94 –74 –77 –104 n/a –82

dBc

GND

= | V

- V

| V

ODpp

= 2· V

Definition V

Definition for Output

Non-Inverting Clock

Inverting Clock

ODpp

GND

= | V

- V

| V

IDpp

= 2· V

Definition V

Definition for Input

Non-Inverting Clock

Inverting Clock

IDpp

LMK04610

ZHCSG17B –JANUARY 2017–REVISED JULY 2019

www.ti.com.cn

8 Parameter Measurement Information

8.1 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions, causing confusion

when reading data sheets or communicating with other engineers. This section addresses the measurement and

description of a differential signal so the reader is able to understand and distinguish between the two different

definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and noninverting signal. The symbol for this first measurement is typically V

or V

, depending on if

an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the noninverting signal

with respect to the inverting signal. The symbol for this second measurement is V

and is a calculated

parameter; this signal does not exist in the IC with respect to ground, it only exists in reference to its differential

pair. V

can be measured directly by oscilloscopes with floating references, otherwise this value can be

calculated as twice the value of V

as described in the first description.

Figure 9 illustrates the two different definitions side-by-side for inputs and Figure 10 illustrates the two different

definitions side-by-side for outputs. The V

and V

definitions show V

and V

DC levels that the noninverting

and inverting signals toggle between with respect to ground. V

input and output definitions show that if the

inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now

increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the

differential signal can be measured.

and V

are often defined as volts (V) and V

is often defined as volts peak-to-peak (V

Figure 9. Two Different Definitions for

Differential Input Signals

Figure 10. Two Different Definitions for

Differential Output Signals

Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for

more information.

8.2 Output Termination Scheme

This section describes the test loads setup during device characterization.

8.2.1 HSDS 4/6/8mA

Available on CLKoutX/CLKoutX* and OSCout/OSCout*. When OSCout is programmed for differential output from

OSCin, the OSCout signal will be inverted from input.

PARA

≤ 3 pF

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