7
TCAN4420
www.ti.com.cn
ZHCSH93 –DECEMBER 2017
Copyright © 2017, Texas Instruments Incorporated
AC and DC Electrical Characteristics (continued)
All typical values are at 25°C and supply voltages of V
CC
= 5 V. R
L
= 60 Ω over operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
C
I
Input capacitance to ground (CANH or
CANL)
TXD = V
CC
= V
IO
40 pF
C
ID
Differential input capacitance 20 pF
R
ID
Differential input resistance 20 80 kΩ
R
IN
Single Ended Input resistance
(CANH or CANL)
10 40 kΩ
R
IN(M)
Input resistance matching:
[1 – (R
IN(CANH)
/ R
IN(CANL)
)] × 100 %
V
(CAN_H)
= V
(CAN_L)
= 5 V –1% 1%
V
IO
PIN
V
IO
Supply voltage on V
IO
pin 2.8 5.5 V
I
IO
Supply current on V
IO
pin
RXD pin floating, TXD = 0 V 350 µA
RXD pin floating, TXD = 5 50 µA
TXD Terminal (CAN Transmit Data Input)
V
IH
High-level input voltage 0.7V
IO
V
V
IL
Low-level input voltage 0.3V
IO
V
I
IH
High-level input leakage current V
TXD
= V
IO
= V
CC
= 5.5 V –2.5 0 1 µA
I
IL
Low-level input leakage current V
TXD
= 0 V, V
CC
= 5.5 V –200 –6 µA
I
LKG(OFF)
Unpowered leakage current V
TXD
= 5.5 V, V
IO
= V
CC
= 0 V –1 0 1 µA
C
I
Input Capacitance
V
IN
= 0.4 x sin(2 x M x 2 x 10
6
x t) + 2.5
20 pF
RXD Pin (CAN Receive Data Output)
V
OH
High-level input voltage See 图 10, I
O
= –2 mA 0.8V
IO
V
V
OL
Low-level input voltage See 图 10, I
O
= –2 mA 0.2V
IO
V
I
LKG(OFF)
Unpowered leakage current V
RXD
= 5.5 V, V
IO
= V
CC
= 0 V –1 0 1 µA
SW Pin (Polarity Switch Input)
V
IH
High-level input voltage 0.7V
IO
V
V
IL
Low-level input voltage 0.3V
IO
V
I
IH
High-level input leakage current SW = V
IO
= V
CC
= 5.5 V 0.5 20 µA
I
IL
Low-level input leakage current SW = 0 V, V
CC
= 5.5 V –1 1 µA
I
LKG(OFF)
Unpowered leakage current SW = 5.5 V, V
IO
= V
CC
= 0 V –1 0 1 µA
(1) The TXD dominant time out (t
TXD_DTO
) disables the driver of the transceiver once the TXD has been dominant longer than t
TXD_DTO
,
which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit
dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it
limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst
case, where five successive dominant bits are followed immediately by an error frame. This, along with the t
TXD_DTO
minimum, limits the
minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t
TXD_DTO
= 11 bits / 1.2 ms = 9.2 kbps.
6.8 Timing Requirements
MIN NOM MAX UNIT
Switching Characteristics
t
pHR
Propagation delay time,
high TXD to Driver Recessive
See 图 9,
Typical Conditions for DS: R
L
=
60 Ω, C
L
= 100 pF, R
CM
= open
50
ns
t
pLD
Propagation delay time,
low TXD to Driver Dominant
40
t
sk(p)
Pulse skew (|t
pHR
- t
pLD
|) 10
t
R
Differential output signal rise time 25
t
F
Differential output signal fall time 25
t
TXD_DTO
Dominant time out
(1)
See 图 13, R
L
= 60 Ω, C
L
= open 1.2 4 ms