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首页KS22/KS20系列芯片参考手册
KS22/KS20系列芯片参考手册
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更新于2024-07-17
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“KS22P100M120SF0RM.pdf”是Freescale(现为NXP半导体)发布的KS22系列微控制器的数据手册,适用于开发参考。该手册涵盖了MKS22FN256VLL12、MKS22FN256VLH12、MKS22FN256VFT12等多款型号的芯片,以及MKS20系列的部分型号。文档版本为Rev.3,发布日期为2016年5月。
数据手册的内容结构清晰,包含了多个章节,旨在提供全面的技术信息。以下是手册的主要内容概览:
第1章“关于本手册”:
1.1部分介绍了手册的目标读者群体,主要面向需要使用KS22/KS20系列芯片进行产品开发的工程师。
1.2部分说明了手册的组织结构,帮助读者快速定位所需信息。
1.3部分详细阐述了模块描述,包括如何处理芯片特定信息,例如当芯片特定信息更新或引用不同章节时的处理方式。
1.4部分涉及寄存器描述,是理解微控制器功能的关键。
1.5部分介绍了手册中的约定,包括数字系统、排版符号和特殊术语的使用规则。
第2章“介绍”:
2.1概述了KS22系列芯片的基本特点。
2.2列出了Kinetis KS系列的主要功能特性,强调了Cortex-M4内核的优势。
2.3提供了芯片的Block Diagram,显示了各个模块之间的物理连接和功能布局。
2.4详细划分了模块的功能类别:
- ARM Cortex-M4核心模块:包括处理器内核、浮点运算单元等关键部件。
- 系统模块:如中断控制器、电源管理等支持功能。
- 内存和内存接口:涵盖闪存、SRAM及其他存储解决方案。
- 时钟系统:描述了芯片的时钟源和分频器配置。
- 其他功能模块,可能包括模拟电路、通信接口等。
此外,数据手册还可能继续深入探讨每个模块的具体功能、操作模式、寄存器配置、时序图、电气特性、引脚配置、功耗分析、封装信息以及应用示例等内容。对于开发者来说,这些详细信息至关重要,能够帮助他们充分理解和利用KS22系列芯片的各种特性和性能,以设计出高效、可靠的嵌入式系统。
Section number Title Page
23.2 Modes of operation....................................................................................................................................................... 384
23.3 Memory map/register definition................................................................................................................................... 385
23.3.1 TCD memory............................................................................................................................................... 385
23.3.2 TCD initialization........................................................................................................................................ 385
23.3.3 TCD structure...............................................................................................................................................385
23.3.4 Reserved memory and bit fields...................................................................................................................386
23.3.1 Control Register (DMA_CR).......................................................................................................................397
23.3.2 Error Status Register (DMA_ES)................................................................................................................ 400
23.3.3 Enable Request Register (DMA_ERQ)....................................................................................................... 402
23.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................404
23.3.5 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 406
23.3.6 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 407
23.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................408
23.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................409
23.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................410
23.3.10 Set START Bit Register (DMA_SSRT)...................................................................................................... 411
23.3.11 Clear Error Register (DMA_CERR)............................................................................................................412
23.3.12 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 413
23.3.13 Interrupt Request Register (DMA_INT)......................................................................................................414
23.3.14 Error Register (DMA_ERR)........................................................................................................................ 416
23.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................ 419
23.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................422
23.3.17
Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 424
23.3.18
TCD Source Address (DMA_TCDn_SADDR)...........................................................................................425
23.3.19
TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................425
23.3.20
TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................426
23.3.21
TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 427
23.3.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................428
KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016
16 NXP Semiconductors
Section number Title Page
23.3.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 429
23.3.24
TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................430
23.3.25
TCD Destination Address (DMA_TCDn_DADDR)...................................................................................431
23.3.26
TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................431
23.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................432
23.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 433
23.3.29
TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 434
23.3.30
TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 435
23.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................437
23.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 438
23.4 Functional description...................................................................................................................................................439
23.4.1 eDMA basic data flow................................................................................................................................. 439
23.4.2 Fault reporting and handling........................................................................................................................442
23.4.3 Channel preemption..................................................................................................................................... 445
23.4.4 Performance................................................................................................................................................. 445
23.5 Initialization/application information........................................................................................................................... 449
23.5.1 eDMA initialization..................................................................................................................................... 449
23.5.2 Programming errors..................................................................................................................................... 451
23.5.3 Arbitration mode considerations..................................................................................................................452
23.5.4 Performing DMA transfers.......................................................................................................................... 452
23.5.5 Monitoring transfer descriptor status........................................................................................................... 456
23.5.6 Channel Linking...........................................................................................................................................458
23.5.7 Dynamic programming................................................................................................................................ 459
Chapter 24
External Watchdog Monitor (EWM)
KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016
NXP Semiconductors 17
Section number Title Page
24.1 Chip-specific Information for this Module...................................................................................................................465
24.1.1 EWM clocks.................................................................................................................................................465
24.1.2 EWM low-power modes.............................................................................................................................. 465
24.1.3 EWM_OUT pin state in low power modes..................................................................................................465
24.2 Introduction...................................................................................................................................................................466
24.2.1 Features........................................................................................................................................................ 466
24.2.2 Modes of Operation..................................................................................................................................... 467
24.2.3 Block Diagram............................................................................................................................................. 468
24.3 EWM Signal Descriptions............................................................................................................................................ 468
24.4 Memory Map/Register Definition.................................................................................................................................469
24.4.1 Control Register (EWM_CTRL)................................................................................................................. 469
24.4.2 Service Register (EWM_SERV)..................................................................................................................470
24.4.3 Compare Low Register (EWM_CMPL)......................................................................................................470
24.4.4 Compare High Register (EWM_CMPH).....................................................................................................471
24.4.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................472
24.5 Functional Description..................................................................................................................................................472
24.5.1 The EWM_out Signal.................................................................................................................................. 472
24.5.2 The EWM_in Signal.................................................................................................................................... 473
24.5.3 EWM Counter..............................................................................................................................................474
24.5.4 EWM Compare Registers............................................................................................................................ 474
24.5.5 EWM Refresh Mechanism...........................................................................................................................474
24.5.6 EWM Interrupt.............................................................................................................................................475
24.5.7 Counter clock prescaler................................................................................................................................475
Chapter 25
Watchdog timer (WDOG)
25.1 Chip-specific Information for this Module...................................................................................................................477
25.1.1 WDOG clocks..............................................................................................................................................477
25.1.2 WDOG low-power modes........................................................................................................................... 477
25.2 Introduction...................................................................................................................................................................478
KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016
18 NXP Semiconductors
Section number Title Page
25.3 Features.........................................................................................................................................................................478
25.4 Functional overview......................................................................................................................................................479
25.4.1 Unlocking and updating the watchdog.........................................................................................................481
25.4.2 Watchdog configuration time (WCT)..........................................................................................................482
25.4.3 Refreshing the watchdog..............................................................................................................................483
25.4.4 Windowed mode of operation......................................................................................................................483
25.4.5 Watchdog disabled mode of operation.........................................................................................................483
25.4.6 Debug modes of operation........................................................................................................................... 483
25.5 Testing the watchdog.................................................................................................................................................... 484
25.5.1 Quick test..................................................................................................................................................... 485
25.5.2 Byte test........................................................................................................................................................485
25.6 Backup reset generator..................................................................................................................................................486
25.7 Generated resets and interrupts.....................................................................................................................................487
25.8 Memory map and register definition.............................................................................................................................487
25.8.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 488
25.8.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 490
25.8.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................490
25.8.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................491
25.8.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 491
25.8.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 492
25.8.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 492
25.8.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................492
25.8.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 493
25.8.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 493
25.8.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 494
25.8.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 494
25.9 Watchdog operation with 8-bit access.......................................................................................................................... 494
25.9.1 General guideline......................................................................................................................................... 494
25.9.2 Refresh and unlock operations with 8-bit access.........................................................................................495
KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016
NXP Semiconductors 19
Section number Title Page
25.10 Restrictions on watchdog operation..............................................................................................................................496
Chapter 26
Multipurpose Clock Generator (MCG)
26.1 Chip-specific Information for this Module...................................................................................................................499
26.1.1 MCG oscillator clock input options.............................................................................................................499
26.1.2 MCG Instantiation Information................................................................................................................... 499
26.2 Introduction...................................................................................................................................................................500
26.2.1 Features........................................................................................................................................................ 500
26.2.2 Modes of Operation..................................................................................................................................... 503
26.3 External Signal Description.......................................................................................................................................... 504
26.4 Memory Map/Register Definition.................................................................................................................................504
26.4.1 MCG Control 1 Register (MCG_C1)...........................................................................................................505
26.4.2 MCG Control 2 Register (MCG_C2)...........................................................................................................506
26.4.3 MCG Control 3 Register (MCG_C3)...........................................................................................................507
26.4.4 MCG Control 4 Register (MCG_C4)...........................................................................................................508
26.4.5 MCG Control 5 Register (MCG_C5)...........................................................................................................509
26.4.6 MCG Control 6 Register (MCG_C6)...........................................................................................................510
26.4.7 MCG Status Register (MCG_S).................................................................................................................. 512
26.4.8 MCG Status and Control Register (MCG_SC)............................................................................................513
26.4.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................ 515
26.4.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................515
26.4.11 MCG Control 7 Register (MCG_C7)...........................................................................................................515
26.4.12 MCG Control 8 Register (MCG_C8)...........................................................................................................516
26.4.13 MCG Control 12 Register (MCG_C12).......................................................................................................517
26.4.13 MCG Status 2 Register (MCG_S2)............................................................................................................. 517
26.4.13 MCG Test 3 Register (MCG_T3)................................................................................................................ 518
26.5 Functional description...................................................................................................................................................518
26.5.1 MCG mode state diagram............................................................................................................................ 518
26.5.2 Low-power bit usage....................................................................................................................................522
KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016
20 NXP Semiconductors
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