ASX340 CMOS传感器开发手册：低功耗图像SOC

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镁光ASX340是一款专为便携式和消费电子设备设计的高性能1/4英寸彩色CMOS数码图像传感器，适用于NTSC和PAL制式的数字视频应用。这款集成式图像流处理器(IFP)和视频编码器的SoC（系统级芯片）提供了低功耗性能，适合对电池寿命敏感的产品。其主要特点包括： 1. **光学格式与分辨率**：传感器尺寸为1/4英寸，具备VGA分辨率（640x480像素），这使其在小型设备上提供清晰的图像质量。 2. **图像增强功能**：通过2x的放大功能，用户可以实现精细的图像调整，包括水平和垂直方向的移动控制。同时，它还提供了±40列和±36行的校正功能，用于补偿镜头安装时可能出现的精度误差。 3. **电源选项**：ASX340支持单个2.8V电源供电，并通过外部旁路晶体管实现更灵活的电源配置，适应不同设计要求。 4. **动态图形叠加**：内置的overlay generator允许实时叠加动态位图信息，如图标、徽标或数据，增强了用户的交互体验。 5. **视频编码与处理**：该传感器配备集成的视频编码器，支持NTSC和PAL标准，并具有10位I-DAC（模拟数字转换器），保证了高保真度的视频输出。IFP能执行复杂图像处理任务，如色彩恢复、校正、锐化、伽马校准、镜头阴影校正、缺陷修复、自动白平衡和曝光控制。 6. **自动校准**：自动黑水平校准功能确保了在各种光照条件下，图像都能保持一致的显示效果。 7. **技术文档**：文档来源于Aptina Imaging Corporation，最新资料请访问其官方网站www.aptina.com，以获取最准确的产品规格和更新信息。 ASX340凭借其集成性和高性能，广泛应用于各类消费电子产品，如智能手机摄像头、行车记录仪、监控摄像头和小型摄像机等，满足了对图像质量、功耗和成本效益要求较高的应用需求。

PDF: 3899044103 /Source: 3618915053 .

ASX340CS_DS Rev. B Pub. 4/12 EN

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

Aptina Confidential and Proprietary

Pin Assignments

Pin 1 is not populated with a ball. That allows the device to be identified by an additional

marking.

Table 5: Pin Assignments

1 2 3 4 5 6 7 8

AEXTCLK

GPIO13 DAC_REF VDD DOUT0VDD VDD_PLL

BXTAL VDD_IO

DOUT_LSB1 VAA GND DOUT2DOUT1VDD_IO

CGPIO12 DOUT_LSB0

TCK TRST_N GND DOUT4DOUT3VDD_IO

D GND RESET_BAR

TDI SPI_SCLK GND DOUT6DOUT5VDD

EFRAME_SYNC SADDR

VDD_IO SPI_SDI AGND PIXCLK VDD VDD_IO

FSCLK SDATA

TMS AGND DAC_POS ATEST2 FRAME_VALID DOUT7

GVDD TDO

DD VREG_BASE DAC_NEG ATEST1 LINE_VALID VDD_IO

H GND SPI_CS_N

SPI_SDO Reserved VDD_DAC VAA VAA_PIX VDD_IO

Table 6: Reset/Default State of Interfaces

Name Reset State Default State Notes

EXTCLK Clock running or stopped Clock running

Input

XTAL N/A N/A

Input

RESET_BAR Asserted De-asserted

Input

CLK N/A N/A

Input. Must always be driven to high via

a pull-up resistor in the range of 1.5 to 4.7 kΩ.

DATA High impedance High impedance

Input/Output. Must always be driven to high via

a pull-up resistor in the range of 1.5 to 4.7 kΩ.

ADDR N/A N/A

Input. Must be permanently tied to VDD_IO or

GND.

SPI_SCLK High impedance. Driven, logic 0

Output. Output enable is R0x0032[13].

SPI_SDI Internal pull-up enabled. Internal pull-up enabled

Input. Internal pull-up is permanently enabled.

SPI_SDO High impedance Driven, logic 0

Output enable is R0x0032[13].

SPI_CS_N High impedance Driven, logic 1

Output enable is R0x0032[13].

FRAME_VALID High impedance High impedance

Input/Output. This interface disabled by default.

Input buffers (used for GPIO function) powered

down by default, so these pins can be left

unconnected (floating). After reset, these pins

are powered up, sampled, then powered down

again as part of the auto-configuration

mechanism. See Note 2.

LINE_VALID

PIXCLK High impedance Driven, logic 0

Output. This interface disabled by default.

See Note 1.

OUT7

OUT6

OUT5

OUT4

OUT3

DOUT2

OUT1

OUT0

PDF: 3899044103 /Source: 3618915053 .

ASX340CS_DS Rev. B Pub. 4/12 EN

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

Aptina Confidential and Proprietary

Notes: 1. The reason for defining the default state as logic 0 rather than high impedance is this: when wired in a

system (for example, on Aptina’s demo boards), these outputs will be connected, and the inputs to

which they are connected will want to see a valid logic level. No current drain should result from driving

these to a valid logic level (unless there is a pull-up at the system level).

2. These pads have their input circuitry powered down, but they are not output-enabled. Therefore, they

can be left floating but they will not drive a valid logic level to an attached device.

OUT_LSB1 High impedance High impedance

Input/Output. This interface disabled by default.

Input buffers (used for GPIO function) powered

down by default, so these pins can be left

unconnected (floating). After reset, these pins

are powered-up, sampled, then powered down

again as part of the auto-configuration

mechanism.

OUT_LSB0 High impedance HIgh impedance

DAC_POS High impedance Driven

Output. Interface disabled by hardware reset

and enabled by default when the device starts

streaming.

DAC_NEG

DAC_REF

TDI Internal pull-up enabled Internal pull-up enabled

Input. Internal pull-up means that this pin can

be left unconnected (floating).

TDO High impedance High impedance

Output. Driven only during appropriate parts of

the JTAG shifter sequence.

TMS Internal pull-up enabled Internal pull-up enabled

Input. Internal pull-up means that this pin can

be left unconnected (floating).

TCK Internal pull-up enabled Internal pull-up enabled

Input. Internal pull-up means that this pin can

be left unconnected (floating).

TRST_N N/A N/A

Input. Must always be driven to a valid logic

level. Must be driven to GND for normal

operation.

FRAME_SYNC N/A N/A

Input. Must always be driven to a valid logic

level. Must be driven to GND if not used.

GPIO12 High impedance High impedance

Input/Output. This interface disabled by default.

Input buffers (used for GPIO function) powered

down by default, so these pins can be left

unconnected (floating).

GPIO13 High impedance High impedance

Input/Output. This interface disabled by default.

Input buffers (used for GPIO function) powered

down by default, so these pins can be left

unconnected (floating).

ATEST1 N/A N/A

Must be driven to GND for normal operation.

ATEST2 N/A N/A

Must be driven to GND for normal operation.

Table 6: Reset/Default State of Interfaces (continued)

Name Reset State Default State Notes

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