商品多核下高性能数据包处理：挑战与未来路径
98 浏览量
更新于2024-07-14
收藏 1.1MB PDF 举报
随着新型网络服务的兴起，如电子商务、社交媒体和在线视频，对程序可编程性的需求变得越来越迫切。为了满足这些需求并缩短产品上市时间，商业多核CPU在数据包处理中得到了广泛应用。然而，现有的多核处理器在数据包处理性能上与传统专为网络处理设计的硬件，如Network Processor (NP)之间存在着显著差距。这篇名为《迈向商品多核上的高性能数据包处理：当前问题和未来方向》的研究论文发表于2015年12月的《中国科学：信息科学》(Science China Information Sciences)，卷号58，第120103期，DOI:10.1007/s11432-015-5484-6。
文章首先探讨了当前面临的挑战，包括如何优化多核架构以充分利用多核心资源，以及如何设计高效的软件和硬件协同机制，以提高数据包处理的吞吐量和效率。多核处理器的并行计算能力虽提供了灵活性，但并发控制、数据一致性问题以及线程间通信等挑战使得实现高效数据包处理并非易事。同时，由于多核CPU的指令集复杂性和传统NP的专用硬件设计之间的差异，性能瓶颈可能出现在软件层面。
作者TANG Lu、YAN Jin Li、SUN Zhi Gang、LI Tao 和 ZHANG Min Xuan，来自国防科技大学计算机学院，他们在文中深入分析了这些问题，并提出了潜在的解决方案。这可能包括：
1. **多核优化算法**：通过改进调度策略和算法，如任务分割、负载均衡和动态调整，以减少数据包处理过程中的上下文切换和等待时间。
2. **硬件加速**：探索利用GPU或FPGA进行特定数据包处理操作的加速，比如深度包检查或加密解密，以减轻CPU的压力。
3. **专用网络处理单元**：在多核系统中集成轻量级的网络处理引擎，与通用核心协作，提高处理性能。
4. **软件与硬件协同**：开发更高效的编程模型和API，允许开发者更容易地编写能充分利用硬件特性的代码。
5. **研究新的架构和协议**：针对多核环境，研究新的网络协议和体系结构设计，如虚拟化技术或基于软件定义网络(SDN)的解决方案。
6. **性能评估与基准测试**：建立严格的性能评估标准，以便在设计和优化过程中量化改进，确保性能提升的同时保持良好的能量效率。
这篇论文关注的是将多核技术应用于数据包处理领域的挑战和机遇，旨在推动该领域向着更高的性能和更低的延迟迈进，以适应不断增长的网络服务需求。
Tang L,etal. SciChinaInfSci December 2015 Vol. 58 120103:4
page
Page length 4K
Base address of page
Memory
Directory
Offset
…
Page
Directory
+
Page i
CPU
L1 TLB
L2 TLB
Pipeline
Virtual
Address
Physical address
(a)
SKB
SKB 1
SKB 2
SKB 3
Pkt buffer
Pkt
Data
…
frag_list
frag[0]
…
Header data
SKB Buff
Cache
Slab
allocator
SKB Buffer
Allocation
list
s_mom
free
Slab
descriptor
…
Allocated
object
Cache
Date
Cache
(b)
Figure 2 Virtual-to-physical address translation and SKB allocation. (a) Virtual to physical address translation; (b) SKB
allocation.
relationship of virtual-to-physical address translation), then by the physical address, CPU will directly
look up in L1 and L2 cache or the memory to get the target data. If TLB misses, CPU will turn to look up
in L2 TLB. (3) If TLB hits in L2 TLB, then CPU will directly look up in L1 and L2 cache or the memory
to get the target data by the physical address. If TLB misses, then CPU will look up the memory page
table to obtain the physical addresses and update TLB. Cache access is similar to TLB access, and the
virtual-to-physical address translation is illustrated as in Figure 2(a). It is generally considered that packet
processing only contains two memory access (SKB memory access and data memory access) overheads. In
fact, CPU processing involves many memory accesses: SKB allocation memory access, SKB deallocation
memory access, Slab allocation memory access, Slab deallocation memory access, SKB memory access
and data memory access, etc. In this paper, we mainly investigate SKB allocation memory access.
For example, when Linux system allocates SKB, OS will ask SKB Buffer Management program to
allocate it. SKB Buffer Management will get skbuff from SKB buffer cache (this buffer was allocated by
Slab allocator), and then it gets data buffer from the data cache, and connects the data buffer address to
skbuff, finally returns the allocated SKB to SKB Buffer Management. SKB is composed of skbuff area
and data area. Skbuff consists of objects allocated by slab allocator; the processing is like this: when
there is no allocated objects in SKB buffer cache, SKB Buffer Management will call Slab allocator to
allocate an object. Firstly, slab allocator looks up the Slab allocation table (Slab allocation table stores
the current object status of the assigned page), and then allocates the unallocated object from one slab if
there is still unallocated object in the partial entry. Otherwise, if objects are all allocated, slab allocator
will take a free slab from an unallocated one and allocate it, and add the unallocated slab into the partial
entry set eventually, as shown in Figure 2(b).
The virtual-to-physical address translation overhead and the buffer management overhead are involved
in many complex processes and memory access operations, thus occupying a large portion of packet
processing overheads, and that is why researchers try to optimize these two overheads.
3 Current optimization solutions
To reduce the two overheads and optimize the packet processing performance, a lot of methods have been
proposed in recent years. These methods can be classified into two categories. One is via software, in
which, only software is employed to optimize packet processing (for example: packet reception, and buffer
management, etc.). The other is via hardware, in which, researchers try to modify CPU architecture or
adopt an embedded coprocessor to improve the performance.
剩余15页未读，继续阅读
2021-01-19 上传
2011-12-29 上传
2011-01-28 上传
2023-05-25 上传
2023-07-25 上传
2023-06-12 上传
2024-01-04 上传
2023-02-11 上传
2023-08-14 上传
weixin_38716460
- 粉丝: 4
- 资源: 928
我的内容管理
展开
最新资源
- 最优条件下三次B样条小波边缘检测算子研究
- 深入解析：wav文件格式结构
- JIRA系统配置指南：代理与SSL设置
- 入门必备：电阻电容识别全解析
- U盘制作启动盘：详细教程解决无光驱装系统难题
- Eclipse快捷键大全：提升开发效率的必备秘籍
- C++ Primer Plus中文版：深入学习C++编程必备
- Eclipse常用快捷键汇总与操作指南
- JavaScript作用域解析与面向对象基础
- 软通动力Java笔试题解析
- 自定义标签配置与使用指南
- Android Intent深度解析：组件通信与广播机制
- 增强MyEclipse代码提示功能设置教程
- x86下VMware环境中Openwrt编译与LuCI集成指南
- S3C2440A嵌入式终端电源管理系统设计探讨
- Intel DTCP-IP技术在数字家庭中的内容保护
