SN65DSI85 MIPI DSI to FlatLink LVDS转换桥接器

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"TI-SN65DSI85.pdf 是一份关于MIPI DSI到FlatLink转换器的技术文档，该转换器由德州仪器(TI)制造，型号为SN65DSI85。它是一种双通道MIPI DSI接收器，能够将MIPI DSI接口的数据转换为FlatLink LVDS信号，适用于高清视频流和图形显示应用。" 这篇文档详细介绍了SN65DSI85的功能和特性，包括： 1. 兼容性：SN65DSI85支持MIPI D-PHY 1.00.00及DSI 1.02.00标准，确保与MIPI生态系统内的多种设备兼容。 2. 双通道配置：该器件可以配置为处理1到4条D-PHY数据信道，每通道最高可达1Gbps的数据速率，以适应不同带宽需求。 3. 视频流格式：支持RGB666和RGB888格式，提供18位和24位色彩深度的视频流，适用于高分辨率显示，如WQXGA和WUXGA。 4. 多种操作模式：支持DSI的ODD/EVEN和LEFT/RIGHT操作模式，以及将双通道DSI转换为两条单链路LVDS的模式，增加了灵活性。 5. LVDS输出：LVDS输出时钟可在25MHz至154MHz范围内调整，适应不同系统需求。同时，LVDS像素时钟可以使用D-PHY时钟或外部参考时钟。 6. 能耗优化：采用1.8V主电源，具有关断模式、低LVDS输出电压摆幅、共模控制等低功耗特性，并支持MIPI的超低功耗状态(ULPS)。 7. PCB设计友好：提供LVDS通道交换(SWAP)和引脚顺序反向功能，简化PCB布线。 8. 稳定性与保护：具备ESD防护，额定值±2kV（人体模型），增强产品可靠性。 9. 技术支持：文档还包括技术资料、软件工具和社区支持，便于开发人员获取更多信息和解决问题。 SN65DSI85是为连接MIPI DSI源，如手机、平板电脑等设备的显示接口，转换为FlatLink LVDS信号，以驱动LCD或OLED显示屏的高效解决方案。其高性能、低功耗和灵活配置特性使得它在高清显示和图形应用中具有广泛的应用潜力。

SN65DSI85

www.ti.com.cn

ZHCSAT8F –SEPTEMBER 2012–REVISED JUNE 2018

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

(3) Tested at V

= 1.8V , T

= -40°C for MIN, T

= 25°C for TYP, T

= 85°C for MAX.

FLATLINK LVDS OUTPUT

Steady-state differential output voltage

A_Y x P/N and B_Y x P/N

CSR 0x19.3:2=00 and, or CSR

0x19.1:0=00

100Ω near end termination

180 245 313

CSR 0x19.3:2=01 and, or CSR

0x19.1:0=01

100Ω near end termination

215 293 372

CSR 0x19.3:2=10 and, or CSR

0x19.1:0=10

100Ω near end termination

250 341 430

CSR 0x19.3:2=11 and, or CSR

0x19.1:0=11

100Ω near end termination

290 389 488

CSR 0x19.3:2=00 and, or CSR

0x19.1:0=00

200Ω near end termination

150 204 261

CSR 0x19.3:2=01 and, or CSR

0x19.1:0=01

200Ω near end termination

200 271 346

CSR 0x19.3:2=10 and, or CSR

0x19.1:0=10

200Ω near end termination

250 337 428

CSR 0x19.3:2=11 and, or CSR

0x19.1:0=11

200Ω near end termination

300 402 511

Steady-state differential output voltage for

A_CLKP/N and B_CLKP/N

CSR 0x19.3:2=00 and/or CSR

0x19.1:0=00

near end termination

140 191 244

CSR 0x19.3:2=01 and, or CSR

0x19.1:0=01

100Ω near end termination

168 229 290

CSR 0x19.3:2=10 and, or CSR

0x19.1:0=10

100Ω near end termination

195 266 335

CSR 0x19.3:2=11 and, or CSR

0x19.1:0=11

100Ω near end termination

226 303 381

CSR 0x19.3:2=00 and, or CSR

0x19.1:0=00

200Ω near end termination

117 159 204

CSR 0x19.3:2=01 and, or CSR

0x19.1:0=01

200Ω near end termination

156 211 270

CSR 0x19.3:2=10 and, or CSR

0x19.1:0=10

200Ω near end termination

195 263 334

CSR 0x19.3:2=11 and, or CSR

0x19.1:0=11

200Ω near end termination

234 314 399

Δ|V

Change in steady-state differential output

voltage between opposite binary states

RL = 100Ω 35 mV

OC(SS)

Steady state common-mode output

voltage

(3)

CSR 0x19.6 = 1 and CSR 0x1B.6 = 1;

and, or CSR 0x19.4 = 1 and

CSR 0x1B.4 = 1; see Figure 2

0.8 0.9 1

CSR 0x19.6 = 0 and, or CSR 0x19.4 = 0;

see Figure 2

1.15 1.25 1.35

OC(PP)

Peak-to-peak common-mode output

voltage

see Figure 2 35 mV

LVDS_DIS

Pull-down resistance for disabled LVDS

outputs

1 kΩ

Low Power (LP)

Mode Receiver

LP-RX

Input LOW

LP-RX

Input HIGH

1.3V

VIH-LP

GND

VIL-LP

VIH-HS

High Speed (HS) Mode

Receiver

HS-RX

Common Mode

Range

VCM-HS(MAX)

VCM-HS(MIN)

VID

VIL-HS

SN65DSI85

ZHCSAT8F –SEPTEMBER 2012 –REVISED JUNE 2018

www.ti.com.cn

(1) All typical values are at V

= 1.8 V and T

= 25°C

(2) For EMI reduction purpose, SN65DSI85 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK input.

The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N and/or B_CLKP/N.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

DSI

DSI LP glitch suppression pulse width 300 ps

Skew time from DSI Channel A to Channel B in dual DSI

operation

See Figure 17

LVDS

Output clock period 6.49 40 ns

High-level output clock (CLK) pulse duration 4/7 t

Delay time, CLK↑ to 1st serial bit position

= 6.49 ns;

Input clock jitter < 25 ps

(REFCLK)

–0.15 0.15 ns

Delay time, CLK↑ to 2nd serial bit position 1/7 t

– 0.15 1/7 t

+ 0.15 ns

Delay time, CLK↑ to 3rd serial bit position 2/7 t

– 0.15 2/7 t

+ 0.15 ns

Delay time, CLK↑ to 4th serial bit position 3/7 t

– 0.15 3/7 t

+ 0.15 ns

Delay time, CLK↑ to 5th serial bit position 4/7 t

– 0.15 4/7 t

+ 0.15 ns

Delay time, CLK↑ to 6th serial bit position 5/7 t

– 0.15 5/7 t

+ 0.15 ns

Delay time, CLK↑ to 7th serial bit position 6/7 t

– 0.15 6/7 t

+ 0.15 ns

Differential output rise-time

see Figure 3 180 500 ps

Differential output fall-time

LVDS CLK A to CLK B skew –10 10 ps

EN, ULPS, RESET

Enable time from EN or ULPS t

c(o)

= 12.9 ns 1 ms

dis

Disable time to standby t

c(o)

= 12.9 ns 0.1 ms

reset

Reset Time 10 ms

REFCLK

REFCLK Freqeuncy. Supported frequencies:

25 MHz - 15 4MHz

25 154 MHz

, t

REFCLK rise and fall time 100ps 1ns s

REFCLK Peak-to-Peak Phase Jitter 50 ps

Duty REFCLK Duty Cycle 40% 50% 60%

REFCLK or DSI CLK (DACP/N, DBCP/N)

SSC_CLKIN

SSC enabled Input CLK center spread depth

(2)

0.5% 1% 2%

Modulation Frequency Range 30 60 kHz

Figure 1. DSI Receiver Voltage Definitions

剩余51页未读，继续阅读

不觉明了

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