A Modeling and Mapping Method for Coarse/Fine Mixed-grained
Reconfigurable Architecture
Zhaotong Li, Zheng Huang, Shuai Chen, Xuegong Zhou
*
, Wei Cao and Lingli Wang
State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
* Email: zhouxg@fudan.edu.cn
Abstract
With the advantage of making reasonable trade-offs
between performance and flexibility, reconfigurable
architectures have drawn increasing attention. Automatic
tools for mapping applications to reconfigurable
architectures, however, are rather complicated and
challenging work for the reason that mapping tool is
always subject to the specific reconfigurable architecture.
In this paper, we explore a general modeling and
mapping method for coarse/fine mixed-grained
reconfigurable architectures (MGRAs) by reinventing
the packing method in traditional FPGA software flow
and propose a novel modeling method that can describe
both fine and coarse reconfigurable architecture in XML
format. After a detailed explanation of our proposed
modeling and mapping method, we verify our method by
implementing a mapping tool for a reconfigurable
architecture and manage to map FFT as an application on
it. The experiments demonstrate that our proposed
method can be applied to MGRA modeling and mapping
and is flexible enough to be extended to other
reconfigurable architectures.
1. Introduction
Reconfigurable technology is currently a hot topic in
integrated circuit design field as it has proven its
advantage in flexibility and performance
[1]
. Different
reconfigurable architectures are classified by their grain
of reconfigurability as fine-grained reconfigurable
architectures, coarse-grained reconfigurable architectures
and mixed-grained reconfigurable architectures.
Fine-grained ones are reconfigurable in bit-level and
more flexible. FPGA, for example, is a representative of
fine-grained reconfigurable architectures. Coarse-grained
ones are reconfigurable in word-level, data-driven, less
flexible than fine-grained ones but with better
performance in domain-specific applications.
Coarse/fine mixed-grained reconfigurable architectures
(MGRAs) are a combination of fine/coarse-grained
reconfigurable architectures, which take the advantage of
fine-grained ones as control logic and coarse-grained
ones as datapath for intensive computation.
Reconfigurable architectures are expected to be of
potential in extensive applications such as digital signal
processing, multi-media and encryption/decryption.
However, the lack of effective mapping tools limits the
development of MGRAs to a large extent
[2]
which is
caused by the following reasons. First, traditional
mapping tools for reconfigurable architectures,
especially coarse-grained ones, are largely subject to the
specific architecture of the design. Thus, it is costly and
error-prone to port mapping tools between different
reconfigurable architectures. Also, modeling
reconfigurable array is time-consuming work and there
is not a unified format for describing both fine and
coarse grain architecture. Second, for some
reconfigurable architectures which contain processors, it
is necessary for mapping tool to accomplish some
task-scheduling job in order to realize software and
hardware co-designs. In these scenarios, high-level
language like C language is used input description and
then compiled into an intermediate format like DFG
(Data Flow Graph)
[3]
. Finally, tasks are assigned to
processors and reconfigurable array. This task scheduling
and compilation work is quite a challenging problem and
many large-scale applications have to be mapped
manually
[4]
.
In this paper, we attempt to develop a general modeling
and mapping method under the scenario that
reconfigurable architecture is composed of
coarse-grained and fine-grained units without processors.
Based on this premise, we describe the modeling and
mapping problem from a general perspective. Then, we
come up with our modeling and mapping solution,
conduct a case study by apply our method to a specific
architecture and finally map applications on them. The
main contributions of this paper are as follows.
We propose a modeling and mapping method that is
applicable for both fine and coarse grained
reconfigurable architecture. The mapping method
can be separated from a specific architecture by
modeling different architectures in a unified format.
We adopt a mapping method for MGRAs that is
compatible for traditional fine-grained ones, such as
FPGAs. Correspondingly, the cost of developing
mapping tool software can be reduced for it
encourages the reuse of existing software.
2. Problem Description
978-1-4673-2475-5/12/$31.00 ©2012 IEEE