BQ769X0系列锂离子电池监控器编程手册：功能与保护特性

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"BQ769X0编程手册是一份详细的技术文档，针对BQ76920、BQ76930和BQ76940系列电池监控芯片，专为锂离子和磷酸铁锂电池应用设计。这份手册提供了丰富的功能介绍和规格信息。首先，该产品具有先进的功能，包括纯数字接口，使得与主机微控制器的通信更为高效。内置的ADC能够测量每个电池单元的电压、芯片内部温度以及外部热敏电阻，同时还有一个独立的ADC作为电荷计数器，跟踪电池组的总电流。设计上支持多达三个热敏电阻，提高了系统的温度感知能力。在硬件保护方面，BQ769X0系列提供了多种关键保护机制，如过电流在放电（OCD）条件下的保护，短路在放电（SCD）的检测，过电压（OV）和欠电压（UV）的防护，以及对次级保护器故障的诊断，确保了电池系统的安全运行。此外，集成的细胞均衡FETs确保了电池组中各单元的电压平衡，而低侧NCH驱动器则用于高效的充电和放电控制。当达到预设阈值时，内置的报警中断功能会通知主机微控制器，便于及时处理相关事件。值得注意的是，这份文档强调了生产数据的重要性，并且在文档结尾处包含了关于可用性、保修政策、安全关键应用使用注意事项、知识产权声明以及其他重要免责声明。除非特别注明，否则文档中的所有信息均适用于生产环境。对于软件工具和支持，手册可能包含配套的开发工具包、驱动程序和示例代码，以帮助开发者快速集成和调试BQ769X0系列芯片。同时，文档也涉及社区支持部分，提供用户论坛、技术问答、更新日志等内容，以便用户在使用过程中获取帮助和分享经验。 BQ769X0编程手册是电子工程师在设计和优化锂离子或磷酸铁锂电池管理系统时不可或缺的参考资料，涵盖了从硬件设计到软件集成的全方位指导。"

bq76920, bq76930, bq76940

SLUSBK2G –OCTOBER 2013–REVISED MAY 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: bq76920 bq76930 bq76940

(1) The Absolute Maximum Ratings for (TS1–VSS) apply after the device completes POR and should be observed after t

BOOTREADY

(10 ms), following the application of the boot signal on TS1. Prior to completion of POR, TS1 should not exceed 5 V.

6 Specifications

6.1 Absolute Maximum Ratings

Over-operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

BAT

Supply voltage

(BAT–VSS) bq76920

–0.3 36 V(BAT–VC5x), (VC5x–VSS) bq76930

(BAT–VC10x), (VC10x–VC5x), (VC5x–VSS) bq76940

Input voltage

(VCn–VSS) where n = 1..5 bq76920

–0.3 (n × 7.2) V

(VCn–VSS) where n = 1..5, (VCn-VC5x) where n =

6..10

bq76930

(VCn–VSS) where n = 1..5, (VCn–VC5x) where n =

6..10, (VCn–VC10x) where n = 11..15

bq76940

Cell input pins, differential (VCn–VCn–1) where n = 1..15/10/5

(bq76940/bq76930/bq76920, respectively)

–0.3 9 V

SRN, SRP, SCL, SDA

–0.3 3.6

(VC0–VSS), (CAP1–VSS), (TS1–VSS)

(1)

bq76920

(VC0–VSS), (VC5b–VC5x), (CAP2–VC5x),

(CAP1–VSS), (TS2–VC5x), (TS1–VSS)

(1)

bq76930

(VC0–VSS), (VC5b–VC5x), (VC10b–VC10x),

(CAP3–VC10x), (CAP2–VC5x), (CAP1–VSS),

(TS3–VC10x), (TS2–VC5x), (TS1–VSS)

(1)

bq76940

REGSRC –0.3 36

Output voltage

REGOUT, ALERT –0.3 3.6

VDSG –0.3 20

CHG –0.3 V

CHGCLAMP

Cell balancing current (per cell)

bq76920 70 mA

bq76930,

bq76940

5 mA

DSG

Discharge pin input current when disabled (measured into terminal) 7 mA

STG

Storage temperature –65 150

°C

Lead temperature (soldering, 10 s) 300

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic

discharge

Human body model (HBM) ESD stress voltage

(1)

±2 kV

Charged device model (CDM) ESD stress voltage

(2)

±500 V

6.3 Recommended Operating Conditions

Over-operating free-air temperature range (unless otherwise noted). See Section 8.1.1 for more information on cell

configurations. All voltages are relative to VSS, except "Cell input differential."

MIN TYP MAX UNIT

BAT

Supply voltage

(BAT–VSS) bq76920

6 25 V

(BAT–VC5x), (VC5x–VSS) bq76930

(BAT–VC10x), (VC10x–VC5x),

(VC5x–VSS)

bq76940

bq76920, bq76930, bq76940

SLUSBK2G –OCTOBER 2013–REVISED MAY 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: bq76920 bq76930 bq76940

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ

, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R

θJA

, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ

, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R

θJA

, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

6.4 Thermal Information

Over-operating free-air temperature range (unless otherwise noted)

THERMAL METRIC

(1)

TSSOP

UNIT

bq76920xy

20 PINS (PW)

bq76930xy

30 PINS (DBT)

bq76940xy

44 PINS (DBT)

θJA, High K

Junction-to-ambient thermal resistance

(2)

93.7 86.5 70.1 °C/W

θJC(top)

Junction-to-case(top) thermal resistance

(3)

28.7 19.4 17.5 °C/W

θJB

Junction-to-board thermal resistance

(4)

44.6 41.3 33.9 °C/W

Junction-to-top characterization parameter

(5)

1.3 0.5 0.5 °C/W

Junction-to-board characterization parameter

(6)

44.1 40.6 33.4 °C/W

θJC(bottom)

Junction-to-case(bottom) thermal resistance

(7)

n/a n/a n/a °C/W

6.5 Electrical Characteristics

Typical conditions are measured at 25ºC with nominal BAT voltages of 18 V (bq76920), 36 V (bq76930), or 48 V (bq76940)

with V

CELL

= 4 V. Min and max values include full recommended operating condition temperature range from –40ºC to +85 ºC.

Certain characteristics may be shown at different voltage or temperature ranges, as clarified in the Test Condition sections.

PARAMETER TEST CONDITION MIN TYP MAX UNIT

SUPPLY CURRENTS

NORMAL mode: ADC off,

CC off

Sum of ICC_BAT and ICC_REGSRC

currents

40 60

µA

NORMAL mode: ADC on,

CC off

60 90

NORMAL mode: ADC off,

CC on

110 165

NORMAL mode: ADC on,

CC on

130 195

CC_BAT

NORMAL mode: ADC off

Into BAT pin

30 45

NORMAL mode: ADC on 50 75

CC_REGSRC

NORMAL mode: CC off

Into REGSRC pin

10 15

NORMAL mode: CC on 80 120

SHIP

SHIP/SHUTDOWN mode

Device in full shutdown, only

VSTUP/BG and BOOT detector on

0.6 1.8

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