Intel IXP1200网络处理器数据手册：高性能与灵活性

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Intel IXP1200网络处理器数据手册提供了对高性能处理能力和灵活性的深入理解，适用于各种局域网（LAN）和电信产品。这款处理器的核心特性是集成ASIC硬件与微处理器的可编程性，使其在多个应用领域展现出显著优势。在多层交换机中，IXP1200凭借其强大的ASIC硬件支持，能够高效处理数据包转发和路由，实现高速、低延迟的通信。它支持多种协议，如TCP/IP、IPX/SPX等，使电信产品具备高度的适应性和兼容性。对于宽带电缆设备，IXP1200的性能使得它成为理想的解决方案，能够提供高速带宽管理和质量保证。远程访问设备，如VPDN（虚拟专用网络）接入点或家庭路由器，也得益于其强大的处理能力来支持大量的并发连接和安全功能。智能PCI适配器的设计中，IXP1200的嵌入式StrongARM核心处理器扮演了关键角色。这款32位低功耗RISC处理器具有高运算性能，配备16KB指令缓存和8KB数据缓存，以及一个512B的快速小缓存，用于临时存储不常用但又必须立即访问的数据。此外，还有写缓冲区、内存管理单元，以及通过ARM AHB总线访问其他关键组件，如FBI（Field-Programmable Bus Interface）、PCI接口和SDRAM。六个集成的可编程微引擎是IXP1200的另一个亮点。每个微引擎工作频率高达232MHz，支持四线程操作，实现了单周期算术逻辑运算和移位操作，从而降低了上下文切换的开销。其庞大的寄存器集包括128个通用寄存器和128个传输寄存器，以及2Kx32位的指令控制流水线，确保了执行效率和并行任务的处理能力。 Intel IXP1200网络处理器凭借其卓越的性能、低功耗设计、广泛的协议支持和高度的灵活性，使得它成为构建高性能、可靠且可扩展的网络和电信设备的理想选择。其集成的硬件和微处理器特性使得它在多个应用场景中都能提供卓越的用户体验和高效能表现。

Intel

IXP1200 Network Processor

16 Datasheet

5.4.1 SDRAM Unit

The IXP1200 provides an SDRAM Unit to access low cost, high bandwidth memory for mass data

storage. The StrongARM* core address space allows up to 256 Mbytes of SDRAM to be

addressed. The SDRAM interface operates at half the core frequency (0.5*F

core

), providing a peak

bandwidth of 928 Mbytes per second at 232 MHz.

Bus cycles are generated by requests from the PCI Unit including PCI DMA cycles, the

StrongARM* core, and the Microengines.

The SDRAM is operated by commands that are loaded into command queues within the unit. The

SDRAM Unit decodes the command, reads or writes the data, then deletes the command from the

head of the queue. The read and write sources may be SDRAM memory locations, transfer

registers, or the Transmit and Receive FIFOs in the FBI Unit. Refer to the IXP1200 Network

Processor Family Hardware Reference Manual for details on how these requests are queued,

prioritized, and serviced by the SDRAM Unit.

SDRAM should have an access time (t

) of 6 ns or less (CAS latency = 2), PC100 compatible.

Figure 3 details the major components of the SDRAM Unit.

The SDRAM Bus consists of 15 row/column address bits, 64 data bits, RAS#, CAS#, write enable,

DQM control, and a synchronous output clock running at one-half the IXP1200 core frequency

(0.5*F

core

The PCI, Microengines, and StrongARM* core require single byte, word, and longword write

capabilities. The SDRAM Unit supports this using a read-modify-write technique. As data is

written from the PCI or StrongARM* core to SDRAM, a quadword is read from SDRAM. The

Figure 3. SDRAM Unit Block Diagram

A7013-03

AMBA[31:0]

(from

StrongARM

Core)

Microengine

Commands &

Addresses

Microengine Data [63:0]

SDRAM

up to

256 MB

SDRAM

Interface

Command

Decoder

& Address

Generator

Service Priority

(Arbitration)

Machine & Registers

AMBA Bus

Interface

Logic

AMBA Address

Rd/Wr Queue

PCI Address

RD/Wr Queue

Microengine Address

& Command Queues

(High Priority, Even,

Odd & Order)

Memory/

AMBA Data

FIFO

Adr[14:0]

Data[63:0]

WE#,RAS#

CAS#, DQM

addr

data

SDCLK

PCI Commands

and Addresses

* StrongARM is a registered trademark of ARM Limited.

** ARM architecture compatible

Intel

IXP1200 Network Processor

18 Datasheet

5.4.4 SRAM Unit

The IXP1200 provides an SRAM Unit for very high bandwidth memory for storage of lookup

tables and other data for the packet processing Microengines. The SRAM Unit controls the SRAM

(up to 8 Mbytes), BootROM (up to 8 Mbytes) for booting, and 2 Mbytes of SlowPort address space

for peripheral device access. The I/O signal timing is determined by internal address decodes and

configuration registers for the BootROM and SlowPort address regions. The SRAM Unit includes

an 8 entry Push/Pop register list for fast queue operations, bit test, set and clear instructions for

atomic bit operations, and an 8 entry CAM for Read Locks.

The SRAM interface operates at one-half the IXP1200 core frequency (0.5 * F

core

The SRAM Unit supports both Pipelined Burst Double Cycle Deselect (DCD) and Flowthru

SRAM types. Other SSRAM devices, including single cycle deselect, are not supported. The bus is

also used to attach BootROM and can be used to interface other peripheral devices such as custom

interface logic or MAC management ports. The SRAM interface provides three separate timing

domains for the three device types: SRAM, BootROM, and Peripheral (also referred to as SlowPort

access).

BootROM devices may be either 32 bits or 16 bits in width. This is determined by GPIO[3] during

reset. When 16-bit BootROM devices are used, the maximum BootROM address space is reduced

from 8 Mbytes to 4 Mbytes.

Figure 4 details the major components of the SRAM Unit.

The SRAM Bus consists of 19 address bits, 32 data bits, 4 chip enable bits, 8 buffer and read/write

control signals, a synchronous output clock (SCLK) running at one-half the IXP1200 core

frequency, and a synchronous input clock (SCLKIN). When using Flowthru SRAM types, it is

recommended to route the SCLK signal from the SRAMs back to the SCLKIN input. Routing this

Figure 4. SRAM Unit Block Diagram

A7014-02

AMBA[31:0]

(from

StrongARM

Core)

Microengine

Commands &

Addresses

Microengine Data [63:0]

SRAM

32KB to

8MB

Pipelined-

DCD or

Flowthru

Buffer

SRAM

Interface

Command

Decoder

& Address

Generator

Service Priority

(Arbitration)

Machine & Registers

AMBA Bus

Interface

Logic

AMBA Address

Rd/Wr Queue

Microengine Address

& Command Queues

(High Priority, Read,

Readlock Fail

and Order)

Memory/

AMBA Data

FIFO

Addr[18:0]

Data[31:0]

RD/WR/EN

Signals

addr

data

* StrongARM is a registered trademark of ARM Limited.

** ARM architecture compatible

BootROM

256KB

8 MB

Peripheral

Device

(i.e., MAC

CPU port)

SCLK

Intel

IXP1200 Network Processor

Datasheet 19

trace identically to the DQ data signals will skew the SCLKIN slightly to track the return data trace

propagation delay. When using Pipelined/DCD SRAMs, the SCLKIN input is not used and may be

held inactive with a pulldown to GND to save power.

The SRAM Unit receives memory requests from seven sources: the StrongARM* core and each of

the six Microengines. Refer to the IXP1200 Hardware Reference Manual for details on the

prioritization and queues provided for servicing these requests.

The IXP1200 supports the use of an optional asynchronous ready input for flexibility in interfacing

memory-mapped I/O devices to the SRAM Slowport region. This will allow the I/O device to add

wait-states to IXP1200 I/O accesses. This function is supported on the HIGH_EN#/RDY# pin. An

I/O device must drive HIGH_EN#/RDY# with a wired-OR open drain buffer configuration, and

only drive the pin when the I/O device is selected.

To use the RDY# pin function, it must be enabled by setting SRAM_CSR[19]=1. The RDY# Pause

State Value field located in register SRAM_SLOW_CONFIG[23:16] must be programmed with

the state value at which you choose to pause the internal wait-state logic. This pause state relates to

the other timing parameters programmed into the SRAM_SLOW_CONFIG and

SRAM_SLOWPORT_CONFIG register fields. See Figure 73 which illustrates this example. The

SCC value is the total number of core clocks for the I/O cycle, and the SRWA, SCEA, SRWD, and

SCED values specify the RD/WR and Chip Enable signal assert and deassert times. When the I/O

cycles begins, the SCC value is loaded into the internal state counter and is decremented on each

core clock tick (twice the SCLK frequency). When the state counter reaches the RDY# Pause State

Value, it will remain in that state until the HIGH_EN#/RDY# pin is sampled LOW, allowing the

state counter to resume its decrement operation. The HIGH_EN#/RDY# must be driven for at least

two SCLK periods to be sampled properly by the IXP1200.

The RDY# Pause State must also occur at a minimum of 5 core clock periods prior to the SRWD

state to be recognized. A RDY# Pause State value of SRWD+5 (Decimal 10, Hexidecimal A) is

used in this example.

In this example, 6 additional core clock “wait-states” are inserted. If the RDY# input is

synchronous to SCLK and it meets the specified setup and hold times, the resulting number of wait

states will be predictable. However, if the RDY# input is asynchronous to SCLK, the number of

wait-states the IXP1200 inserts could vary by +/- 2 core clock periods.

5.4.4.1 SRAM Types Supported

Pipeline Burst DCD (double cycle deselect) type: tKQmax=4.2 ns, 3.3 V.

Flowthru type: tKQmax= 9 ns, 3.3 V.

Note: Other SSRAM devices, including single cycle deselect, are not supported.

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