Cyclone II 设备手册：完整版3.3V设计指南

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《Cyclone II 设备手册》是一份由Altera Corporation发布的专业文档，它详细介绍了Cyclone II系列FPGA（现场可编程门阵列）的特性、设计指南和技术细节。该手册的第1卷专为CII5V1-3.3版本设计，针对的是位于101 Innovation Drive, San Jose, CA 95134的公司总部。Altera Corporation是全球知名的可编程解决方案提供商，其商标如Cyclone II品牌、特定器件型号以及其他标识符均为其在美国及国际上的注册或受保护的品牌和服务标记。手册涵盖了广泛的主题，包括但不限于Cyclone II FPGA的架构、布线标准、逻辑单元设计、输入输出接口、配置选项、电源管理、时钟系统、以及设计工具的使用。此外，它还包含了关于设计流程、IP核集成、性能优化、功耗管理和散热策略等内容，旨在帮助工程师们有效地利用这些器件进行硬件设计。在版权方面，Altera Corporation声明所有权利，并保留随时对产品和服务进行更新的权利，而无需提前通知。用户在应用或使用手册中提供的信息、产品或服务时，应严格按照Altera的书面协议行事。同时，Altera建议客户获取最新的产品规格和应用支持，以确保设计的兼容性和最佳性能。安全性和合规性也是手册关注的重点，Altera对半导体产品的性能保修符合标准，但在没有明确书面同意的情况下，不承担因应用或使用手册内容产生的任何责任或义务。由于涉及知识产权和专利保护，对于其他产品和服务名称，除非特别注明，否则它们属于各自的持有者。《Cyclone II Device Handbook》是一部深入理解Cyclone II系列FPGA的关键资源，为电子设计工程师提供了全面的设计参考和支持，无论是在新项目启动、现有设计升级还是技术研究中，都具有重要的实用价值。

Section I–2 Altera Corporation

Preliminary

Revision History Cyclone II Device Handbook, Volume 1

Altera Corporation 1–1

February 2008

1. Introduction

Introduction

Following the immensely successful first-generation Cyclone

device

family, Altera

Cyclone II FPGAs extend the low-cost FPGA density

range to 68,416 logic elements (LEs) and provide up to 622 usable I/O

pins and up to 1.1 Mbits of embedded memory. Cyclone II FPGAs are

manufactured on 300-mm wafers using TSMC's 90-nm low-k dielectric

process to ensure rapid availability and low cost. By minimizing silicon

area, Cyclone II devices can support complex digital systems on a single

chip at a cost that rivals that of ASICs. Unlike other FPGA vendors who

compromise power consumption and performance for low-cost, Altera’s

latest generation of low-cost FPGAs—Cyclone II FPGAs, offer 60% higher

performance and half the power consumption of competing 90-nm

FPGAs. The low cost and optimized feature set of Cyclone II FPGAs make

them ideal solutions for a wide array of automotive, consumer,

communications, video processing, test and measurement, and other

end-market solutions. Reference designs, system diagrams, and IP, found

at www.altera.com, are available to help you rapidly develop complete

end-market solutions using Cyclone II FPGAs.

Low-Cost Embedded Processing Solutions

Cyclone II devices support the Nios II embedded processor which allows

you to implement custom-fit embedded processing solutions. Cyclone II

devices can also expand the peripheral set, memory, I/O, or performance

of embedded processors. Single or multiple Nios II embedded processors

can be designed into a Cyclone II device to provide additional

co-processing power or even replace existing embedded processors in

your system. Using Cyclone II and Nios II together allow for low-cost,

high-performance embedded processing solutions, which allow you to

extend your product's life cycle and improve time to market over

standard product solutions.

Low-Cost DSP Solutions

Use Cyclone II FPGAs alone or as DSP co-processors to improve

price-to-performance ratios for digital signal processing (DSP)

applications. You can implement high-performance yet low-cost DSP

systems with the following Cyclone II features and design support:

■ Up to 150 18 × 18 multipliers

■ Up to 1.1 Mbit of on-chip embedded memory

■ High-speed interfaces to external memory

CII51001-3.2

1–2 Altera Corporation

Cyclone II Device Handbook, Volume 1 February 2008

Features

■ DSP intellectual property (IP) cores

■ DSP Builder interface to The Mathworks Simulink and Matlab

design environment

■ DSP Development Kit, Cyclone II Edition

Cyclone II devices include a powerful FPGA feature set optimized for

low-cost applications including a wide range of density, memory,

embedded multiplier, and packaging options. Cyclone II devices support

a wide range of common external memory interfaces and I/O protocols

required in low-cost applications. Parameterizable IP cores from Altera

and partners make using Cyclone II interfaces and protocols fast and easy.

Features

The Cyclone II device family offers the following features:

■ High-density architecture with 4,608 to 68,416 LEs

● M4K embedded memory blocks

● Up to 1.1 Mbits of RAM available without reducing available

logic

● 4,096 memory bits per block (4,608 bits per block including 512

parity bits)

● Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,

and ×36

● True dual-port (one read and one write, two reads, or two

writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes

● Byte enables for data input masking during writes

● Up to 260-MHz operation

■ Embedded multipliers

● Up to 150 18- × 18-bit multipliers are each configurable as two

independent 9- × 9-bit multipliers with up to 250-MHz

performance

● Optional input and output registers

■ Advanced I/O support

● High-speed differential I/O standard support, including LVDS,

RSDS, mini-LVDS, LVPECL, differential HSTL, and differential

SSTL

● Single-ended I/O standard support, including 2.5-V and 1.8-V,

SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI

and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-,

and 1.8-V LVTTL

● Peripheral Component Interconnect Special Interest Group (PCI

SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V

operation at 33 or 66 MHz for 32- or 64-bit interfaces

● PCI Express with an external TI PHY and an Altera PCI Express

×1 Megacore

function

Altera Corporation 1–3

February 2008 Cyclone II Device Handbook, Volume 1

Introduction

● 133-MHz PCI-X 1.0 specification compatibility

● High-speed external memory support, including DDR, DDR2,

and SDR SDRAM, and QDRII SRAM supported by drop in

Altera IP MegaCore functions for ease of use

● Three dedicated registers per I/O element (IOE): one input

● Programmable bus-hold feature

● Programmable output drive strength feature

● Programmable delays from the pin to the IOE or logic array

● I/O bank grouping for unique VCCIO and/or VREF bank

settings

● MultiVolt

™

I/O standard support for 1.5-, 1.8-, 2.5-, and

3.3-interfaces

● Hot-socketing operation support

● Tri-state with weak pull-up on I/O pins before and during

configuration

● Programmable open-drain outputs

● Series on-chip termination support

■ Flexible clock management circuitry

● Hierarchical clock network for up to 402.5-MHz performance

● Up to four PLLs per device provide clock multiplication and

division, phase shifting, programmable duty cycle, and external

clock outputs, allowing system-level clock management and

skew control

● Up to 16 global clock lines in the global clock network that drive

throughout the entire device

■ Device configuration

● Fast serial configuration allows configuration times less than

100 ms

● Decompression feature allows for smaller programming file

storage and faster configuration times

● Supports multiple configuration modes: active serial, passive

serial, and JTAG-based configuration

● Supports configuration through low-cost serial configuration

devices

● Device configuration supports multiple voltages (either 3.3, 2.5,

or 1.8 V)

■ Intellectual property

● Altera megafunction and Altera MegaCore function support,

and Altera Megafunctions Partners Program (AMPP

)

megafunction support, for a wide range of embedded

processors, on-chip and off-chip interfaces, peripheral

functions, DSP functions, and communications functions and

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