STM32C011x4/x6: Arm Cortex-M0+ 32位微控制器数据手册

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"STM32C011x4/STM32C011x6是基于Arm Cortex-M0+内核的32位微控制器，具有32KB闪存和6KB RAM，支持多种通信接口，适用于2-3.6V电压范围的应用。" STM32C011x4/x6系列是意法半导体（ST）推出的高性能、低功耗微控制器，主要针对需要高效能和成本效益的嵌入式应用。这款芯片集成了ST的最新专利技术，确保了卓越的性能和可靠性。 1. 内核与性能： - 采用Arm Cortex-M0+处理器内核，最高工作频率可达48MHz，提供高效处理能力。 - 工作温度范围广泛，覆盖-40°C到85°C，部分型号可扩展至105°C或125°C，适应各种环境条件。 2. 存储器： - 集成32KB闪存，用于存储程序代码，并具备保护功能，防止未经授权的访问。 - 包含6KB的SRAM，带有硬件奇偶校验检查，增强数据完整性。 3. 系统特性： - 电源管理：支持2.0V到3.6V的工作电压范围，具备电源上电/掉电复位（POR/PDR）、可编程brownout复位（BOR），以及多种低功耗模式，如睡眠、停止、待机和关断。 4. 时钟系统： - 提供4到48MHz的晶体振荡器，确保精确的时钟源。 - 配备32kHz晶体振荡器，支持校准，适用于低功耗应用。 - 内建48MHz RC振荡器，精度为±1%，32kHz RC振荡器，精度为±5%。 5. 输入/输出（I/O）： - 提供多达18个快速I/O端口，所有端口均可映射到外部中断向量。 - 全部I/O端口为5V耐受，可在高电压环境中稳定工作。 6. 数据传输： - 3通道DMA控制器，可灵活映射，提高数据传输效率。 7. 模拟特性： - 集成12位ADC，转换速度高达0.4µs，支持最多13个外部输入通道，测量范围0到3.6V。 8. 定时器： - 提供8个定时器，包括16位高级电机控制定时器，满足不同定时和计数需求。 9. 其他特性： - CRC计算单元，用于数据校验。 - 多种通信接口，如USART，方便实现设备间的通信。 STM32C011x4/x6微控制器以其强大的处理能力、丰富的外设和灵活的电源管理方案，适用于需要高效能和低功耗的嵌入式应用，如物联网设备、工业控制、智能家居等。

DS13866 Rev 4 15/92

STM32C011x4/x6 Functional overview

oscillators stop. The HSI48 can be restarted by a peripheral with wake-up capability

requiring HSI48.

The LSE and LSI can be kept running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

The event of exiting Stop mode enables the HSI48 oscillator and select HSISYS as

system clock.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The regulator is switched off to power down V

CORE

domain.

The HSI48 RC oscillator and the HSE crystal oscillator are also powered down. The

RTC is switched off.

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost, except for 16-bit backup

registers whose contents are kept.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wake-up event (WKUP pin, configurable rising or falling edge), or when a failure

is detected on LSE (CSS on LSE).

• Shutdown mode

The BOR is not available in Shutdown mode. No power voltage monitoring is possible

in this mode.

SRAM and register contents are lost.

The device exits Shutdown mode upon external reset event (NRST pin), or wake-up

event (WKUP pin, configurable rising or falling edge).

3.7.5 Reset mode

During and upon exiting reset, the Schmitt triggers of I/Os are disabled so as to reduce

power consumption. In addition, when the reset source is internal, the built-in pull-up

resistor on NRST pin is deactivated.

3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep and Stop

modes.

The Shutdown mode allows to achieve the lowest power consumption. The internal

regulator is switched off to power down the V

CORE

domain. The HSI48 and LSI RC-

oscillators and HSE crystal oscillator are also powered down. The RTC is off.

DS13866 Rev 4 17/92

STM32C011x4/x6 Functional overview

• Peripheral clock sources: several peripherals (I2S, USART1, I2C1, ADC) can

operate with a clock source independent of the system clock.

• Clock security system (CSS): in the event of HSE or LSE clock failure, the system

clock is automatically switched to HSI48 or LSI, respectively. If enabled, a software

interrupt is generated. The CCS feature can be enabled by software.

• Clock output:

– MCO and MCO2 (microcontroller clock output) provides one of the internal

clocks for external use by the application.

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes.

Several prescalers allow the application to configure AHB and APB domain clock

frequencies, 48 MHz at maximum.

3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of

the GPIO pins are shared with special digital or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such

as to avoid spurious writing to I/O control registers.

3.11 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with

single-AHB architecture.

With 3 channels, it performs data transfers between memory-mapped peripherals and/or

memories, to offload the CPU.

Each channel is dedicated to managing memory access requests from one or more

peripherals. The unit includes an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

• Single-AHB master

• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-

peripheral data transfers

• Access, as source and destination, to on-chip memory-mapped devices such as flash

memory, SRAM, and AHB and APB peripherals

• All DMA channels independently configurable:

– Each channel is associated either with a DMA request signal coming from a

peripheral, or with a software trigger in memory-to-memory transfers. This

configuration is done by software.

– Priority between the requests is programmable by software (four levels per

channel: very high, high, medium, low) and by hardware in case of equality (such

as request to channel 1 has priority over request to channel 2).

– Transfer size of source and destination are independent (byte, half-word, word),

emulating packing and unpacking. Source and destination addresses must be

aligned on the data size.

Functional overview STM32C011x4/x6

18/92 DS13866 Rev 4

– Support of transfers from/to peripherals to/from memory with circular buffer

management

– Programmable number of data to be transferred: 0 to 2

- 1

• Generation of an interrupt request per channel. Each interrupt request originates from

any of the three DMA events: transfer complete, half transfer, or transfer error.

3.12 DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the

peripherals and the DMA controller. Each channel selects a unique DMA request line,

unconditionally or synchronously with events from its DMAMUX synchronization inputs.

DMAMUX may also be used as a DMA request generator from programmable events on its

input trigger signals.

3.13 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called

exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)

and an extended interrupt/event controller (EXTI) are the assets contributing to handling the

exceptions. Exceptions include core-internal events such as, for example, a division by zero

and, core-external events such as logical level changes on physical lines. Exceptions result

in interrupting the program flow, executing an interrupt service routine (ISR) then resuming

the original program flow.

The processor context (contents of program pointer and status registers) is stacked upon

program interrupt and unstacked upon program resume, by hardware. This avoids context

stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving

time, code and power. The ability to abandon and restart load-multiple and store-multiple

operations significantly increases the device’s responsiveness in processing exceptions.

3.13.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It

handles physical line events associated with a non-maskable interrupt (NMI) and maskable

interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between

interrupt events and start of corresponding interrupt service routines (ISRs). The ISR

vectors are listed in a vector table, stored in the NVIC at a base address. The vector

address of an ISR to execute is hardware-built from the vector table base address and the

ISR order number used as offset.

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring

just before is waiting for being served, the later-arriving higher-priority interrupt event is

served first. Another optimization is called tail-chaining. Upon a return from a higher-priority

ISR then start of a pending lower-priority ISR, the unnecessary processor context

unstacking and stacking is skipped. This reduces latency and contributes to power

efficiency.

DS13866 Rev 4 19/92

STM32C011x4/x6 Functional overview

Features of the NVIC:

• Low-latency interrupt processing

• 4 priority levels

• Handling of a non-maskable interrupt (NMI)

• Handling of 32 maskable interrupt lines

• Handling of 10 Cortex-M0+ exceptions

• Later-arriving higher-priority interrupt processed first

• Tail-chaining

• Interrupt vector retrieval by hardware

3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and

allows identifying wake-up events at processor wake-up from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising,

and falling edge detector capability. Any GPIO and a few peripheral signals can be

connected to these channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which allows the

software to identify the origin of the processor's wake-up from Stop mode or, to identify the

GPIO and the edge event having caused an interrupt.

3.14 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32C011x4/x6 devices. The

ADC has up to 13 external channels and 2 internal channels (temperature sensor, voltage

reference). It performs conversions in single-shot or scan mode. In scan mode, automatic

conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling

rate of 2.5 MSps even with a low CPU speed. An auto-shutdown function guarantees that

the ADC is powered off except during the active conversion phase.

The ADC can be served by the DMA controller. It can operate in the whole V

supply

range.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all scanned channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to

the ADC start triggers, to allow the application to synchronize A/D conversions with timers.

3.14.1 Temperature sensor

The temperature sensor (TS) generates a voltage V

that varies linearly with temperature.

The temperature sensor is internally connected to an ADC input to convert the sensor

output voltage into a digital value.

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