MAXII EPM570 设备手册：特性与规格

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"MAXII(EPM570)是Altera公司的一款基于MAX II系列的可编程逻辑器件。这款设备的手册提供了设计者所需的数据表规格，涵盖了内部架构、JTAG和在系统编程（ISP）信息、直流操作条件、交流定时参数以及订购信息等关键内容。手册分为多个章节进行详细阐述，包括：引言、MAX II架构、JTAG和在系统编程、热插拔和电源复位在MAX II设备中的应用、直流和切换特性以及参考和订购信息。每个章节都有各自的修订历史，以便用户了解最新更新情况。" MAXII(EPM570)是一款高级的现场可编程门阵列（FPGA），属于Altera公司的MAX II系列。这个系列的器件旨在提供高性能、低功耗和灵活的设计解决方案。EPM570作为其中的一员，拥有丰富的逻辑单元、I/O接口和嵌入式功能，适用于各种电子系统设计。在"MAX II Architecture"章节中，读者可以了解到MAX II器件的内部结构，包括逻辑阵列块（LABs）、可编程乘积项（Look-up Tables，LUTs）、配置存储器、输入/输出单元（IOBs）和其他专用功能模块。这些组件共同构成了一个高度可定制的逻辑平台，允许设计者根据需求配置不同的电路功能。 "JTAG and In-System Programmability"章节详细介绍了MAX II设备的测试访问口（TAP）和JTAG标准，这是设备在系统编程和故障诊断的重要机制。通过JTAG接口，设计者能够在设备已经安装在系统中时对器件进行编程和调试，极大地简化了开发流程和后期维护。 "Hot Socketing and Power-On Reset in MAX II Devices"章节关注的是设备在热插拔和电源复位条件下的行为。在现代电子系统中，设备可能需要在运行时被插入或移除，而热插拔功能确保了这种操作的安全性。电源复位功能则保证了器件在上电时能正确初始化，防止因电源波动引起的问题。 "DC and Switching Characteristics"章节提供了器件的直流特性和开关性能数据，如工作电压范围、电流消耗、输入/输出延迟、驱动能力等。这些参数对于评估MAX II(EPM570)在实际系统中的性能和功耗至关重要。最后，"Reference and Ordering Information"章节包含了订购MAX II(EPM570)及相关组件的详细信息，包括封装选项、温度范围、速度等级以及其他选型指南，帮助设计者根据项目需求选择合适的器件版本。 MAXII(EPM570)及其相关手册为电子设计工程师提供了一套全面的参考资料，从硬件架构到编程方法，再到实际应用中的注意事项，为实现高效、可靠的设计提供了强有力的支持。

2–6 Chapter 2: MAX II Architecture

Logic Elements

MAX II Device Handbook © October 2008 Altera Corporation

Logic Elements

The smallest unit of logic in the MAX II architecture, the LE, is compact and provides

advanced features with efficient logic utilization. Each LE contains a four-input LUT,

which is a function generator that can implement any function of four variables. In

addition, each LE contains a programmable register and carry chain with carry-select

capability. A single LE also supports dynamic single-bit addition or subtraction mode

selectable by an LAB-wide control signal. Each LE drives all types of interconnects:

local, row, column, LUT chain, register chain, and DirectLink interconnects. See

Figure 2–6.

Figure 2–5. LAB-Wide Control Signals

labclkena1

labclk2labclk1

labclkena2

asyncload

or labpre

syncload

Dedicated

LAB Column

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

labclr1

labclr2

synclr

addnsub

Chapter 2: MAX II Architecture 2–7

Logic Elements

Each LE’s programmable register can be configured for D, T, JK, or SR operation. Each

asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any

LE can drive the register’s clock and clear control signals. Either general-purpose I/O

pins or LEs can drive the clock enable, preset, asynchronous load, and asynchronous

data. The asynchronous load data input comes from the data3 input of the LE. For

combinational functions, the LUT output bypasses the register and drives directly to

the LE outputs.

Each LE has three outputs that drive the local, row, and column routing resources. The

LUT or register output can drive these three outputs independently. Two LE outputs

drive column or row and DirectLink routing connections and one drives local

interconnect resources. This allows the LUT to drive one output while the register

drives another output. This register packing feature improves device utilization

because the device can use the register and the LUT for unrelated functions. Another

special packing mode allows the register output to feed back into the LUT of the same

LE so that the register is packed with its own fan-out LUT. This provides another

mechanism for improved fitting. The LE can also drive out registered and

unregistered versions of the LUT output.

Figure 2–6. MAX II LE

labclk1

labclk2

labclr2

labpre/aload

Carry-In1

Carry-In0

LAB Carry-In

Clock and

Clock Enable

Select

LAB Carry-Out

Carry-Out1

Carry-Out0

Look-Up

Ta ble

(LUT)

Carry

Chain

Row, column,

and DirectLink

routing

Row, column,

and DirectLink

routing

Programmable

PRN/ALD

CLRN

ENA

Packed

Chip-Wide

Reset (DEV_CLRn)

labclkena1

labclkena2

Synchronous

Load and

Clear Logic

LAB-wide

Synchronous

Load

LAB-wide

Synchronous

Clear

Asynchronous

Clear/Preset/

Load Logic

data1

data2

data3

data4

LUT chain

routing to next LE

labclr1

Local routing

output

ADATA

addnsub

Feedback

routing from

previous LE

2–8 Chapter 2: MAX II Architecture

Logic Elements

MAX II Device Handbook © October 2008 Altera Corporation

LUT Chain and Register Chain

In addition to the three general routing outputs, the LEs within an LAB have LUT

chain and register chain outputs. LUT chain connections allow LUTs within the same

LAB to cascade together for wide input functions. Register chain outputs allow

registers within the same LAB to cascade together. The register chain output allows an

LAB to use LUTs for a single combinational function and the registers to be used for

an unrelated shift register implementation. These resources speed up connections

between LABs while saving local interconnect resources. Refer to “MultiTrack

Interconnect” on page 2–12 for more information about LUT chain and register chain

connections.

addnsub Signal

The LE’s dynamic adder/subtractor feature saves logic resources by using one set of

LEs to implement both an adder and a subtractor. This feature is controlled by the

LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either

A + B or A – B. The LUT computes addition; subtraction is computed by adding the

two’s complement of the intended subtractor. The LAB-wide signal converts to two’s

complement by inverting the B bits within the LAB and setting carry-in to 1, which

adds one to the least significant bit (LSB). The LSB of an adder/subtractor must be

placed in the first LE of the LAB, where the LAB-wide addnsub signal automatically

sets the carry-in to 1. The Quartus II Compiler automatically places and uses the

adder/subtractor feature when using adder/subtractor parameterized functions.

LE Operating Modes

The MAX II LE can operate in one of the following modes:

■ “Normal Mode”

■ “Dynamic Arithmetic Mode”

Each mode uses LE resources differently. In each mode, eight available inputs to the

LE, the four data inputs from the LAB local interconnect, carry-in0 and carry-

in1 from the previous LE, the LAB carry-in from the previous carry-chain LAB, and

the register chain connection are directed to different destinations to implement the

desired logic function. LAB-wide signals provide clock, asynchronous clear,

asynchronous preset/load, synchronous clear, synchronous load, and clock enable

control for the register. These LAB-wide signals are available in all LE modes. The

addnsub control signal is allowed in arithmetic mode.

The Quartus II software, in conjunction with parameterized functions such as library

of parameterized modules (LPM) functions, automatically chooses the appropriate

mode for common functions such as counters, adders, subtractors, and arithmetic

functions.

2–10 Chapter 2: MAX II Architecture

Logic Elements

The other two LUTs use the data1 and data2 signals to generate two possible carry-out

signals: one for a carry of 1 and the other for a carry of 0. The carry-in0 signal acts

as the carry-select for the carry-out0 output and carry-in1 acts as the carry-

select for the carry-out1 output. LEs in arithmetic mode can drive out registered

and unregistered versions of the LUT output.

The dynamic arithmetic mode also offers clock enable, counter enable, synchronous

up/down control, synchronous clear, synchronous load, and dynamic

adder/subtractor options. The LAB local interconnect data inputs generate the

counter enable and synchronous up/down control signals. The synchronous clear

and synchronous load options are LAB-wide signals that affect all registers in the

LAB. The Quartus II software automatically places any registers that are not used by

the counter into other LABs. The addnsub LAB-wide signal controls whether the LE

acts as an adder or subtractor.

Carry-Select Chain

The carry-select chain provides a very fast carry-select function between LEs in

dynamic arithmetic mode. The carry-select chain uses the redundant carry calculation

to increase the speed of carry functions. The LE is configured to calculate outputs for a

possible carry-in of 0 and carry-in of 1 in parallel. The carry-in0 and carry-in1

signals from a lower-order bit feed forward into the higher-order bit via the parallel

carry chain and feed into both the LUT and the next portion of the carry chain. Carry-

select chains can begin in any LE within an LAB.

Figure 2–8. LE in Dynamic Arithmetic Mode

Note to Figure 2–8:

(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.

data1

LUT

data2

data3

addnsub

(LAB Wide)

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

ALD/PRE

CLRN

ENA

ADATA

connection

LUT

Carry-Out1Carry-Out0

LAB Carry-In

Carry-In0

Carry-In1

(1)

sclear

(LAB Wide)

sload

(LAB Wide)

LUT chain

connection

chain output

Row, column, and

direct link routing

Row, column, and

direct link routing

Local routing

aload

(LAB Wide)

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