MyHDL入门与实践：Python语言驱动的系统级设计教程 - CSDN文库

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《PythonMyHDL.pdf》是一份详细的指南，介绍了如何使用Python语言与MyHDL库进行高级硬件描述语言（Hardware Description Language）的设计和开发。该文档主要分为以下几个部分： 1. **概述** (Chapter 1) 开篇介绍MyHDL的基本概念，旨在为读者提供一个整体的认识，包括MyHDL在Python中的地位和其在硬件设计中的作用。 2. **背景信息** (Chapter 2) - **先决条件**：这部分会列出使用MyHDL所需的基础知识，例如对Python编程的理解，以及对数字信号处理和行为级描述的理解。 - **教程简介**：通过一个小规模的教程，让读者快速上手MyHDL的生成器（generators）功能，这是MyHDL的核心特性之一。 - **装饰器的使用**：解释了如何利用Python的装饰器（decorators）来增强MyHDL代码的灵活性和可重用性。 3. **MyHDL入门** (Chapter 3) - **基础模拟**：演示如何设置和执行基本的MyHDL仿真，涉及信号（signals）、端口（ports）和并发处理的概念。 - **参数和层次结构**：介绍如何在模块化设计中管理参数和组件的层级关系。 - **位操作**：讲解MyHDL中的逻辑运算，如布尔逻辑、移位和比较等。 - **MyHDL与Python结合的总结和前景展望**：讨论了MyHDL如何利用Python的易用性和脚本能力提高硬件设计的效率。 4. **建模技术** (Chapter 4) - **结构化建模**：阐述如何使用MyHDL构建模块化的硬件结构模型。 - **RTL建模**：详细说明针对硬件描述的 Register Transfer Level (RTL) 设计方法。 - **高级建模**：探讨如何使用抽象层来创建更高级别的描述，提升设计的可读性和可维护性。 5. **单元测试** (Chapter 5) - **介绍**：说明单元测试在硬件设计中的重要性，尤其是在验证MyHDL模块的行为。 - **测试开发**：指导用户如何编写和执行针对MyHDL代码的测试用例。 6. **与Verilog协同工作** (Chapter 6) - **介绍**：讲解如何将MyHDL与Verilog进行联合仿真，实现不同硬件描述语言间的协作。 - **HDL侧与MyHDL侧**：分别描述在Verilog和MyHDL环境中的具体实施步骤和限制。 - **实施细节**：提供实施过程中的注意事项和建议。 7. **转换到Verilog和VHDL** (Chapter 7) - **介绍**：简述MyHDL转换为Verilog或VHDL的目的和方法。 - **解决方案描述**：详细解释转换的过程和技术细节。 - **转换特点**：列出支持的功能和可能遇到的问题，如信号列表处理、赋值问题和自定义代码的处理等。 - **用户自定义代码**：强调哪些部分可以被转换，哪些不能，以及如何处理这些非转换部分。《PythonMyHDL.pdf》是一份实用的指南，适合想要学习Python作为硬件描述语言工具的工程师，无论是初学者还是经验丰富的开发者，都能从中获得设计和验证复杂数字电路所需的理论知识和实践技巧。

MyHDL manual, Release 0.6

function is now a generator function with an explicit deﬁnition of the desired behavior. It

is decorated with the instance() decorator. You can see that driveClk() is a generator

function because it contains yield statements.

When a generator function is called, it returns a generator object. This is basically what the

instance() decorator does. It is less sophisticated than the always() decorator, but it can

be used to create a generator from any local generator function.

The yield statement is a general Python construct, but MyHDL uses it in a dedicated way.

In MyHDL, it has a similar meaning as the wait statement in VHDL: the statement suspends

execution of a generator, and its clauses specify the conditions on which the generator should

wait before resuming. In this case, the generator waits for a certain delay.

Note that to make sure that the generator runs “forever”, we wrap its behavior in a while

True loop.

Similarly, we can deﬁne a general Hello() function as follows:

def Hello(clk, to="World!"):

@always(clk.posedge)

def sayHello():

print "%s Hello %s" % (now(), to)

return sayHello

We can create any number of instances by calling the functions with the appropriate param-

eters. Hierarchy can be modeled by deﬁning the instances in a higher-level function, and

returning them. This pattern can be repeated for an arbitrary number of hierarchical levels.

Consequently, the general deﬁnition of a MyHDL instance is recursive: an instance is either a

sequence of instances, or a generator.

As an example, we will create a higher-level function with four instances of the lower-level

functions, and simulate it:

def greetings():

clk1

= Signal(0)

clk2 = Signal(0)

clkdriver_1 = ClkDriver(clk1) # positional and default association

clkdriver_2 = ClkDriver(clk=clk2, period=19) # named association

hello_1 = Hello(clk=clk1) # named and default association

hello_2 = Hello(to="MyHDL", clk=clk2) # named association

return clkdriver_1, clkdriver_2, hello_1, hello_2

inst = greetings()

sim = Simulation(inst)

sim.run(50)

As in standard Python, positional or named parameter association can be used in instanti-

ations, or a mix of both . All these styles are demonstrated in the example above. Named

association can be very useful if there are a lot of parameters, as the argument order in the call

does not matter in that case.

12 Chapter 3. Introduction to MyHDL

MyHDL manual, Release 0.6

The simulation produces the following output:

% python greetings.py

9 Hello MyHDL

10 Hello World!

28 Hello MyHDL

30 Hello World!

47 Hello MyHDL

50 Hello World!

_SuspendSimulation: Simulated 50 timesteps

Warning: Some commonly used terminology has different meanings in Python versus

hardware design. Rather than artiﬁcially changing terminology, I think it’s best to keep it

and explicitly describing the differences. A module in Python refers to all source code in

a particular ﬁle. A module can be reused by other modules by importing. In hardware

design, a module is a reusable block of hardware with a well deﬁned interface. It can

be reused in another module by instantiating it. An instance in Python (and other object-

oriented languages) refers to the object created by a class constructor. In hardware design,

an instance is a particular incarnation of a hardware module.

Normally, the meaning should be clear from the context. Occasionally, I may qualify terms

with the words “hardware” or “MyHDL” to avoid ambiguity.

3.4 Bit oriented operations

3.4.1 The intbv class

Hardware design involves dealing with bits and bit-oriented operations. The standard Python

type int has most of the desired features, but lacks support for indexing and slicing. For this

reason, MyHDL provides the intbv class. The name was chosen to suggest an integer with

bit vector ﬂavor.

intbv works transparently with other integer-like types. Like class int, it provides access to

the underlying two’s complement representation for bitwise operations. However, unlike int,

it is a mutable type. This means that its value can be changed after object creation, through

methods and operators such as slice assignment.

intbv supports the same operators as int for arithmetic. In addition, it provides a number

of features to make it suitable for hardware design. First, the range of allowed values can be

constrained. This makes it possible to check the value at run time during simulation. More-

over, back end tools can determine the smallest possible bit width for representing the object.

Secondly, it supports bit level operations by providing an indexing and slicing interface.

intbv objects are constructed in general as follows:

intbv([val=None] [, min=None] [, max=None])

val is the initial value. min and max can be used to constrain the value. Following the Python

conventions, min is inclusive, and max is exclusive. Therefore, the allowed value range is min

.. max-1.

Let’s us look at some examples. First, an unconstrained intbv object is created as follows:

3.4. Bit oriented operations 13

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