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首页PCI Express Base Specification v4.0: Errata and Updates (Feb 2016)
PCI Express Base Specification v4.0: Errata and Updates (Feb 201...
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PCIExpress (PCIe) 是一种高速接口标准,用于在计算机系统内部和外部设备之间传输数据,它最初由PCI-SIG (Peripheral Component Interconnect Special Interest Group) 提出并维护。该规范的Base Specification旨在定义基础架构和技术规范,以便实现高效、兼容的系统通信。
这份名为"PCIExpress Base Specification Revision 4.0 Version 0.7"的文档发布于2016年2月,标志着PCIe技术的持续发展和标准化过程。从提供的修订历史来看,PCIe的发展经历了多个版本,从最初的1.0版到4.0版,每一步都伴随着关键特性的增加和错误修正。
在早期版本中,如1.0a版,包含了C1-C66和E1-E4.17等批准的错误修正(Errata)和工程变更(ECNs)。随着技术的进步,2.0版引入了5.0 GT/s的数据速率,并继续集成新的错误修正和ECNs,如内部错误报告、多播功能、原子操作等,这些特性提升了系统的可靠性和性能。
2.1版的更新包括了对先前版本错误的整合,如(latency tolerance reporting)延迟容忍度报告和(extended tag enable default)扩展标签启用默认设置,以及其他增强功能的加入,如动态电源分配和ID-based ordering,这有助于优化系统功耗和资源管理。
值得注意的是,修订历史中提到的一些ECNs涉及更深入的技术细节,例如atomic operations(原子操作)确保数据一致性,atomic operations对于防止并发访问冲突至关重要;以及alternative routing-ID interpretation (ARI) ECN,它可能涉及到路由策略的灵活性改进。
到了4.0版本,PCIe的性能和复杂性进一步提升,可能包括更高级的错误检测和恢复机制、更高效的事务处理提示(TLP Processing Hints)以及扩展的前缀(TLPPrefix)等特性。这些改进旨在支持现代计算环境中对带宽、速度和效率的高需求。
PCIExpress Base Specification是一个不断演进的标准,涵盖了从物理层设计、数据传输协议到高级功能的一系列细节。每个新版本的发布都是为了适应技术进步,提升系统性能,并确保所有兼容设备之间的互操作性。使用这份规范,硬件制造商可以开发出与市场上的其他PCIe设备无缝协同工作的硬件产品。
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
16
8.4.2 Electrical Idle........................................................................................................ 1026
8.4.3 EIEOS for M-PCIe ................................................................................................ 1026
8.4.4 Lane Polarity Inversion ........................................................................................ 1026
8.4.5 Fast Training Sequence (FTS) .............................................................................. 1026
8.4.6 LINK Data RATE .................................................................................................. 1027
8.4.7 LINK Width ........................................................................................................... 1027
8.4.8 LANE-to-LANE De-skew ...................................................................................... 1027
8.4.9 LINK Training and Status State Machine (LTSSM) ............................................. 1027
8.4.10 Entry to HIBERN8 ............................................................................................ 1049
8.5 RECEIVER ERROR ....................................................................................................... 1049
8.6 CLOCK TOLERANCE COMPENSATION ......................................................................... 1050
8.7 DYNAMIC LINK BANDWIDTH MANAGEMENT ........................................................... 1050
8.7.1 LINK Rate Series and Speed Management ........................................................... 1050
8.7.2 LINK Width Management ..................................................................................... 1051
8.7.3 Dynamic LINK Re-Configuration ......................................................................... 1051
8.8 M-PHY REGISTERS ................................................................................................... 1054
8.8.1 M-PHY Capability Registers................................................................................. 1054
8.8.2 M-PHY Configuration Attributes .......................................................................... 1061
9 ELECTRICAL SUB-BLOCK ....................................................................................... 1063
9.1 ELECTRICAL SPECIFICATION ORGANIZATION ............................................................ 1063
9.2 INTEROPERABILITY CRITERIA .................................................................................... 1063
9.2.1 Data Rates ............................................................................................................. 1063
9.2.2 Refclk Architectures .............................................................................................. 1063
9.3 TRANSMITTER SPECIFICATION ................................................................................... 1063
9.3.1 Measurement Setup for Characterizing Transmitters........................................... 1063
9.3.2 Voltage Level Definitions ...................................................................................... 1065
9.3.3 Tx Voltage Parameters ......................................................................................... 1066
9.3.4 Transmitter Margining.......................................................................................... 1075
9.3.5 Tx Jitter Parameters ............................................................................................. 1076
9.3.6 Tx and Rx Return Loss .......................................................................................... 1086
9.3.7 Transmitter PLL Bandwidth and Peaking ............................................................ 1088
9.3.8 Data Rate Independent Tx Parameters ................................................................. 1088
9.4 RECEIVER SPECIFICATIONS ........................................................................................ 1090
9.4.1 Receiver Stressed Eye Specification ..................................................................... 1090
9.4.2 Stressed Eye Test................................................................................................... 1095
9.4.3 Common Receiver Parameters ............................................................................. 1102
9.4.4 Low Frequency and Miscellaneous Signaling Requirements ............................... 1105
9.5 CHANNEL TOLERANCING ........................................................................................... 1107
9.5.1 Channel Compliance Testing ................................................................................ 1107
9.6 REFCLK SPECIFICATIONS ........................................................................................... 1116
9.6.1 Refclk Test Setup ................................................................................................... 1116
9.6.2 Data Rate Independent Refclk Parameters ........................................................... 1117
9.6.3 Refclk Architectures Supported............................................................................. 1118
9.6.4 Filtering Functions Applied to Raw Data ............................................................. 1118
9.6.5 Common Refclk Rx Architecture (CC) .................................................................. 1120
9.6.6 Jitter Limits for Refclk Architectures .................................................................... 1123
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
17
10 SR-IOV SPECIFICATION ............................................................................................ 1124
10.1 ARCHITECTURAL OVERVIEW ..................................................................................... 1124
10.1.1 PCI Technologies Interoperability ................................................................... 1136
10.2 INITIALIZATION AND RESOURCE ALLOCATION .......................................................... 1137
10.2.1 SR-IOV Resource Discovery ............................................................................. 1137
10.2.2 Reset Mechanisms ............................................................................................. 1141
10.2.3 IOV Re-initialization and Reallocation ............................................................ 1142
10.2.4 VF Migration .................................................................................................... 1142
10.3 CONFIGURATION ........................................................................................................ 1145
10.3.1 Overview ........................................................................................................... 1145
10.3.2 Configuration Space ......................................................................................... 1146
10.3.3 SR-IOV Extended Capability ............................................................................ 1146
10.3.4 PF/VF Configuration Space Header ................................................................ 1161
10.3.5 PCI Express Capability..................................................................................... 1166
10.3.6 PCI Standard Capabilities ................................................................................ 1174
10.3.7 PCI Express Extended Capabilities .................................................................. 1175
10.4 ERROR HANDLING ..................................................................................................... 1181
10.4.1 Baseline Error Reporting .................................................................................. 1181
10.4.2 Advanced Error Reporting ................................................................................ 1183
10.5 INTERRUPTS ............................................................................................................... 1190
10.5.1 Interrupt Mechanisms ....................................................................................... 1190
10.6 POWER MANAGEMENT ............................................................................................... 1191
10.6.1 VF Device Power Management States .............................................................. 1191
10.6.2 PF Device Power Management States .............................................................. 1191
10.6.3 Link Power Management State ......................................................................... 1192
10.6.4 VF Power Management Capability .................................................................. 1192
SR-IOV ACKNOWLEDGEMENTS ............................................................................................ 1192
11 ATS SPECIFICATION .................................................................................................. 1195
11.1 ARCHITECTURAL OVERVIEW ..................................................................................... 1195
11.1.1 Address Translation Services (ATS) Overview ................................................. 1197
11.1.2 Page Request Interface Extension .................................................................... 1202
11.1.3 Process Address Space ID (PASID) ................................................................. 1204
11.2 ATS TRANSLATION SERVICES ................................................................................... 1205
11.2.1 Memory Requests with Address Type ............................................................... 1205
11.2.2 Translation Requests ......................................................................................... 1206
11.2.3 Translation Completion .................................................................................... 1209
11.2.4 Completions with Multiple Translations ........................................................... 1216
11.3 ATS INVALIDATION ................................................................................................... 1218
11.3.1 Invalidate Request ............................................................................................. 1218
11.3.2 Invalidate Completion ....................................................................................... 1219
11.3.3 Invalidate Completion Semantics ..................................................................... 1221
11.3.4 Request Acceptance Rules................................................................................. 1222
11.3.5 Invalidate Flow Control .................................................................................... 1222
11.3.6 Invalidate Ordering Semantics ......................................................................... 1223
11.3.7 Implicit Invalidation Events .............................................................................. 1224
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
18
11.3.8 PASID TLP Prefix and Global Invalidate ........................................................ 1225
11.4 PAGE REQUEST SERVICES .......................................................................................... 1226
11.4.1 Page Request Message ...................................................................................... 1227
11.4.2 Page Request Group Response Message .......................................................... 1231
11.5 CONFIGURATION ........................................................................................................ 1233
11.5.1 ATS Extended Capability Structure .................................................................. 1233
11.5.2 Page Request Extended Capability Structure ................................................... 1236
ATS ACKNOWLEDGEMENTS .................................................................................................. 1242
A. ISOCHRONOUS APPLICATIONS ................................................................................. 1255
A.1. INTRODUCTION .......................................................................................................... 1255
A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ......................................... 1257
A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ........................... 1258
A.2.2. Isochronous Payload Size ................................................................................. 1259
A.2.3. Isochronous Bandwidth Allocation ................................................................... 1259
A.2.4. Isochronous Transaction Latency ..................................................................... 1260
A.2.5. An Example Illustrating Isochronous Parameters ............................................ 1261
A.3. ISOCHRONOUS TRANSACTION RULES ......................................................................... 1262
A.4. TRANSACTION ORDERING .......................................................................................... 1262
A.5. ISOCHRONOUS DATA COHERENCY ............................................................................. 1262
A.6. FLOW CONTROL ......................................................................................................... 1263
A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION ..................................................... 1263
A.7.1. Isochronous Bandwidth of PCI Express Links.................................................. 1263
A.7.2. Isochronous Bandwidth of Endpoints ............................................................... 1263
A.7.3. Isochronous Bandwidth of Switches ................................................................. 1263
A.7.4. Isochronous Bandwidth of Root Complex......................................................... 1264
A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS ................................................... 1264
A.8.1. An Endpoint as a Requester .............................................................................. 1264
A.8.2. An Endpoint as a Completer ............................................................................. 1264
A.8.3. Switches............................................................................................................. 1265
A.8.4. Root Complex .................................................................................................... 1266
B. SYMBOL ENCODING .................................................................................................... 1267
C. PHYSICAL LAYER APPENDIX .................................................................................... 1276
C.1. 8B/10B DATA SCRAMBLING EXAMPLE ....................................................................... 1276
C.2. 128B/130B DATA SCRAMBLING EXAMPLE ................................................................. 1282
D. REQUEST DEPENDENCIES .......................................................................................... 1285
E. ID-BASED ORDERING USAGE .................................................................................... 1288
E.1. INTRODUCTION .......................................................................................................... 1288
E.2. POTENTIAL BENEFITS WITH IDO USE ........................................................................ 1289
E.2.1. Benefits for MFD/RP Direct Connect ............................................................... 1289
E.2.2. Benefits for Switched Environments ................................................................. 1289
E.2.3. Benefits for Integrated Endpoints ..................................................................... 1290
E.2.4. IDO Use in Conjunction with RO ..................................................................... 1290
E.3. WHEN TO USE IDO .................................................................................................... 1290
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
19
E.4. WHEN NOT TO USE IDO ............................................................................................ 1291
E.4.1. When Not to Use IDO with Endpoints .............................................................. 1291
E.4.2. When Not to Use IDO with Root Ports ............................................................. 1291
E.5. SOFTWARE CONTROL OF IDO USE ............................................................................. 1292
E.5.1. Software Control of Endpoint IDO Use ............................................................ 1292
E.5.2. Software Control of Root Port IDO Use ........................................................... 1293
F. MESSAGE CODE USAGE .............................................................................................. 1294
G. PROTOCOL MULTIPLEXING ................................................................................... 1296
G.1. PROTOCOL MULTIPLEXING INTERACTIONS WITH PCI EXPRESS ................................. 1299
G.2. PMUX PACKETS ........................................................................................................ 1305
G.3. PMUX PACKET LAYOUT ........................................................................................... 1306
G.3.1. PMUX Packet Layout for 8b10b Encoding ...................................................... 1306
G.3.2. PMUX Packet Layout at 128b/130b Encoding ................................................. 1308
G.4. PMUX CONTROL ....................................................................................................... 1311
G.5. PMUX EXTENDED CAPABILITY ................................................................................. 1311
G.5.1. PCI Express Extended Header (Offset 00h) ..................................................... 1312
G.5.2. PMUX Capability Register (Offset 04h) ........................................................... 1313
G.5.3. PMUX Control Register (Offset 08h) ............................................................... 1314
G.5.4. PMUX Status Register (Offset 0Ch) ................................................................. 1316
G.5.5. PMUX Protocol Array (Offsets 10h Through 48h) ........................................... 1319
H. M-PCIE TIMING DIAGRAMS .................................................................................... 1321
H.1. INIT TO L0 .................................................................................................................. 1322
H.2. L0 WITH TRANSMITTER IN STALL ............................................................................ 1323
H.3. L0 TO L1 .................................................................................................................... 1324
H.4. DOWNSTREAM PORT INITIATED LINK BANDWIDTH CHANGE ................................... 1325
H.5. UPSTREAM PORT INITIATED LINK BANDWIDTH CHANGE ......................................... 1326
I. M-PCIE COMPLIANCE PATTERNS ......................................................................... 1327
I.1. RPAT ........................................................................................................................ 1327
I.2. RPAT VARIATION BY LANE ...................................................................................... 1328
I.3. CONTINUOUS MODE CRPAT ..................................................................................... 1328
I.4. BURST MODE CRPAT ............................................................................................... 1329
ACKNOWLEDGEMENTS ...................................................................................................... 1330
PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.7
20
Figures
FIGURE 1-1: PCI EXPRESS LINK .................................................................................................... 59
FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 60
FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 64
FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 66
FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 67
FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER .............................. 72
FIGURE 2-2: SERIAL VIEW OF A TLP ............................................................................................. 75
FIGURE 2-3: GENERIC TLP FORMAT ............................................................................................. 76
FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 77
FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 78
FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 83
FIGURE 2-7: 64-BIT ADDRESS ROUTING ........................................................................................ 85
FIGURE 2-8: 32-BIT ADDRESS ROUTING ........................................................................................ 85
FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 88
FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 88
FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER ....................................................... 89
FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 92
FIGURE 2-13: TRANSACTION ID .................................................................................................... 92
FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 99
FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY ...................... 102
FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ...................... 102
FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS ............................................ 103
FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ...................... 104
FIGURE 2-192: TPH TLP PREFIX ................................................................................................ 105
FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ........................................... 106
FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ........................................... 106
FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER ....................... 108
FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ... 108
FIGURE 2-24: MESSAGE REQUEST HEADER ................................................................................ 110
FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ......................................................... 120
FIGURE 2-26: HEADER FOR PCI-SIG-DEFINED VDMS ................................................................ 121
FIGURE 2-27: LN MESSAGE [TO BE UPDATED] ............................................................................ 123
FIGURE 2-28: DRS MESSAGE ...................................................................................................... 124
FIGURE 2-29: FRS MESSAGE ...................................................................................................... 125
FIGURE 2-30: LTR MESSAGE ...................................................................................................... 127
FIGURE 2-31: OBFF MESSAGE ................................................................................................... 128
FIGURE 2-32: PTM REQUEST/RESPONSE MESSAGE ..................................................................... 129
FIGURE 2-33: PTM RESPONSED MESSAGE (4 DW HEADER AND 1 DW PAYLOAD) ...................... 130
FIGURE 2-34: COMPLETION HEADER FORMAT ............................................................................ 132
FIGURE 2-35: (NON-ARI) COMPLETER ID .................................................................................. 133
FIGURE 2-36: ARI COMPLETER ID .............................................................................................. 133
FIGURE 2-37: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 140
FIGURE 2-38: FLOWCHART FOR SWITCH HANDLING OF TLPS ..................................................... 142
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