AT32UC3B微控制器英文数据手册：高性能、低功耗

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"AT32UC3B英文数据手册提供了关于高性能、低功耗AVR®32UC3 32位微控制器的详细信息，包括其高效单周期RISC指令集、多层总线系统、内部高速闪存和SRAM等特性。" AT32UC3B是Atmel公司推出的一款基于AVR32架构的高性能、低功耗32位微控制器。该芯片设计旨在提供卓越的处理能力和能效，适用于各种嵌入式应用。以下是对标题和描述中提及的知识点的详细说明： 1. **高性能、低功耗AVR®32UC3 32位微控制器**：这个特性意味着AT32UC3B能够在消耗较少功率的同时提供强大的计算能力。它采用紧凑的单周期RISC指令集，支持数字信号处理（DSP）指令，能够实现高达1.39 DMIPS/MHz的性能。在60MHz时钟频率下，可以达到83 DMIPS的运行速度，而在30MHz时钟频率下，可以达到46 DMIPS。 2. **单周期RISC指令集**：RISC（精简指令集计算机）设计使得处理器能在一个时钟周期内执行一条指令，显著提高了执行速度和效率。 3. **读-修改-写指令与原子位操作**：这些功能允许对内存中的数据进行高效修改，而不会引起数据不一致，对于多任务和实时系统的管理至关重要。 4. **多级总线系统**：AT32UC3B拥有高性能的数据传输结构，通过独立的总线提高性能，7个外围DMA通道进一步提升了外围设备通信的速度。 5. **内部高速闪存**：提供512KB、256KB、128KB和64KB四种版本，可实现30MHz下的单周期访问。预取缓冲优化了在最大速度下的指令执行。快速的编程和擦除时间（4ms页编程，8ms全芯片擦除），以及100,000次写入周期和15年的数据保持能力，确保了可靠性和长期稳定性。此外，还包括闪存安全锁定和用户定义配置区域。 6. **内部高速SRAM**：根据闪存容量不同，SRAM大小分别为96KB（512KB闪存）、32KB（256KB和128KB闪存）和16KB（64KB闪存），均支持全速下的单周期访问。 7. **中断控制器**：具备自动向量化的低延迟中断服务，可编程优先级，能够快速响应外部事件，确保实时系统的性能。 8. **系统功能**：未在摘要中详细列出，但通常会包含时钟管理、电源管理、复位控制、调试接口和其他外设接口等功能，以满足复杂系统的各种需求。 AT32UC3B是一款高度集成的微控制器，适合需要高性能、低功耗和丰富外设接口的嵌入式设计。其高效能核心、灵活的内存架构和强大的中断系统使得它成为许多嵌入式应用的理想选择。

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32059H–AVR32–02/10

AT32UC3B

Refer to Section 28.3 on page 615 for decoupling capacitors values and regulator

characteristics.

5.6.2.2 Dual Power Supply

In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent

from leakage current.

To avoid over consumption during the power up sequence, VDDIO and VDDCORE must follow

ramps given Figure 5-3.

Figure 5-3. VDDIO versus VDDCORE during power up sequence

5.6.3 Analog-to-Digital Converter (ADC) reference.

The ADC reference (ADVREF) must be provided from an external source. Two decoupling

capacitors must be used to insure proper decoupling.

Figure 5-4. ADVREF Decoupling

Refer to Section 28.4 on page 615 for decoupling capacitors values and electrical

characteristics.

In case ADC is not used, the ADVREF pin should be connected to GND to avoid extra

consumption.

Extra consumption on VDDCORE

VDDCORE (V)

Extra consumption on VDDIO

VDDIO (V)

0 0.2 0.4 0.6 0.8 1 1.2 1.4

1.6

1.8 2

0.5

1.5

2.5

3.5

ADVREF

VREF1VREF2

3.3V

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AT32UC3B

6. Processor and Architecture

Rev: 1.0.0.0

This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the

AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre-

sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical

Reference Manual.

6.1 Features

• 32-bit load/store AVR32A RISC architecture

– 15 general-purpose 32-bit registers

– 32-bit Stack Pointer, Program Counter and Link Register reside in register file

– Fully orthogonal instruction set

– Privileged and unprivileged modes enabling efficient and secure Operating Systems

– Innovative instruction set together with variable instruction length ensuring industry leading

code density

– DSP extention with saturating arithmetic, and a wide variety of multiply instructions

• 3-stage pipeline allows one instruction per clock cycle for most instructions

– Byte, halfword, word and double word memory access

– Multiple interrupt priority levels

• MPU allows for operating systems with memory protection

6.2 AVR32 Architecture

AVR32 is a high-performance 32-bit RISC microprocessor architecture, designed for cost-sensi-

tive embedded applications, with particular emphasis on low power consumption and high code

density. In addition, the instruction set architecture has been tuned to allow a variety of micro-

architectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance

processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.

Through a quantitative approach, a large set of industry recognized benchmarks has been com-

piled and analyzed to achieve the best code density in its class. In addition to lowering the

memory requirements, a compact code size also contributes to the core’s low power characteris-

tics. The processor supports byte and halfword data types without penalty in code size and

performance.

Memory load and store operations are provided for byte, halfword, word, and double word data

with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely

linked to the architecture and is able to exploit code optimization features, both for size and

speed.

In order to reduce code size to a minimum, some instructions have multiple addressing modes.

As an example, instructions with immediates often have a compact format with a smaller imme-

diate, and an extended format with a larger immediate. In this way, the compiler is able to use

the format giving the smallest code size.

Another feature of the instruction set is that frequently used instructions, like add, have a com-

pact format with two operands as well as an extended format with three operands. The larger

format increases performance, allowing an addition and a data move in the same instruction in a

single cycle. Load and store instructions have several different formats in order to reduce code

size and speed up execution.

32059H–AVR32–02/10

AT32UC3B

Figure 6-2. The AVR32UC Pipeline

6.3.2 AVR32A Microarchitecture Compliance

AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar-

geted at cost-sensitive, lower-end applications like smaller microcontrollers. This

microarchitecture does not provide dedicated hardware registers for shadowing of register file

registers in interrupt contexts. Additionally, it does not provide hardware registers for the return

address registers and return status registers. Instead, all this information is stored on the system

stack. This saves chip area at the expense of slower interrupt handling.

Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These

registers are pushed regardless of the priority level of the pending interrupt. The return address

and status register are also automatically pushed to stack. The interrupt handler can therefore

use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are

restored, and execution continues at the return address stored popped from stack.

The stack is also used to store the status register and return address for exceptions and scall.

Executing the rete or rets instruction at the completion of an exception or system call will pop

this status register and continue execution at the popped return address.

6.3.3 Java Support

AVR32UC does not provide Java hardware acceleration.

6.3.4 Memory Protection

The MPU allows the user to check all memory accesses for privilege violations. If an access is

attempted to an illegal memory address, the access is aborted and an exception is taken. The

MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.

6.3.5 Unaligned Reference Handling

AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is

able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an

address exception. Doubleword-sized accesses with word-aligned pointers will automatically be

performed as two word-sized accesses.

IF ID ALU

MUL

Regfile

write

Pref etch unit Decode unit

ALU unit

Multiply unit

Load-store

unit

Regfile

Read

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