高性能应用的PF8100/PF8200电源管理芯片：集成7 buck转换器与I2C可调参数

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PF8100和PF8200是NXP半导体公司推出的一款专为高性能应用设计的高性能电源管理集成电路（PMIC）。这款PMIC针对i.MX8和S32x系列处理器平台优化，旨在提供高效能的电源解决方案，以满足现代电子设备对能源管理和多路供电的需求。这两个型号的PMIC核心特性包括： 1. 高效能降压转换器：它们集成了多达7个高效能的降压转换器，这些转换器能够在不损失过多能量的情况下，将输入电压降至处理器、内存以及其他外围设备所需的电压水平，从而降低功耗并提高整体系统效率。 2. 线性调节器：还有4个线性调节器，这些线性稳压器可以根据需要提供恒定的电压输出，且支持负载开关选项，能够动态调整输出电流，以适应不同负载条件。 3. 集成RTC电源和电池充电器：提供了实时钟（RTC）供电和内置电池充电功能，确保系统即使在无主电源时也能保持时间同步，并能为备用电池充电。 4. 安全监控与管理：包括看门狗定时器和监视电路，可以实现故障检测和自动恢复，符合ASIL-B级别的安全性要求，增强了系统的稳定性和可靠性。 5. 一次性可编程存储器：内置的非易失性存储器允许用户在出厂前预先配置关键的启动参数，减少了外部元件的数量，简化了系统设计和生产流程。 6. 高速I2C通信接口：3.4MHz的I2C通信接口允许快速设置和调整转换器参数，提高了系统的灵活性，尤其是在不同工作模式下的动态配置。 7. 紧凑封装：PF8100和PF8200采用56-pin 8x8 QFN封装，这种小型化设计有助于节省电路板空间，适合于空间受限的嵌入式和工业级应用。 PF8100和PF8200是高性能PMIC的理想选择，它们在提升系统能效、简化设计、增强安全性和灵活性方面表现出色，广泛应用于各种高性能电子设备中，如物联网设备、消费电子、汽车电子等。

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Product data sheet Rev. 11 — 24 February 2021

16 / 133

The fuse circuits have a CRC error check routine which reports and protects against

corresponding TRIM_NOK or OTP_NOK flag is asserted. See Section 17 "OTP/TBB and

default configurations" for details on handling fuse load errors.

If no fuse load errors are present, VSNVS is configured as indicated in the OTP

configuration bits, and the state machine moves to the LP_OFF state.

13.1.2 LP_Off state

The LP_Off state is a low power off mode selectable by the LPM_OFF bit during

the system on modes. By default, the LPM_OFF = 0 when VIN crosses the UVDET

threshold, therefore the state machine stops at the LP_Off state until a valid power up

event is present. When LPM_OFF= 1, the state machine transitions automatically to the

QPU_Off state if no power up event has been present and waits in the QPU_Off until a

valid power up event is present.

The selection of the LPM_OFF bit is based on whether prioritizing low quiescent current

(stay in LP_Off) or quick power up (move to QPU_Off state).

If a power up event is started in LP_Off state with LPM_OFF = 0 and a fuse loading error

is detected, the PF8100/PF8200 ignores the power up event and remains in the LP_Off

state to avoid any potential damage to the system.

To be in LP_Off state, it is necessary to have VIN present. If a valid LICELL is present,

but VIN is below the UVDET, the PF8100/PF8200 enters the coin cell state.

13.1.3 Self-test routine (PF8200 only)

When device transitions from the LP_Off state, it turns on all necessary internal circuits

as it moves into the self-test routine and performs a self-check routine to verify the

integrity of the internal circuits.

During the self-test routine the following blocks are verified:

• The high speed clock circuit is operating within a maximum of 15 % tolerance

• The output of the voltage generation bandgap and the monitoring bandgap are not

more than 4 % to 12 % apart from each other

• A CRC is performed on the mirror registers during the self-test routine, to ensure the

integrity of the registers before powering up

• ABIST test on all voltage monitors.

To allow for varying settling times for the internal bandgap and clocks, the self-test block

is executed up to 3 times (with 2.0 ms between each test) if a failure is encountered, the

state machine proceeds to the fail-safe transition.

A failure in the ABIST test is not interpreted as a self-test failure and it only sets the

corresponding ABIST flag for system information. The MCU is responsible for reading the

information and deciding whether it can continue with a safe operation. See Section 18.1

"System safety strategy" for more information about the functional safety strategy of

PF8200.

Upon a successful self-test, the state machine proceeds to the QPU_Off state.

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Product data sheet Rev. 11 — 24 February 2021

17 / 133

13.1.4 QPU_Off state

The QPU_Off state is a higher power consumption off mode, in which all internal circuitry

required for a power on is biased and ready to start a power up sequence.

If LPM_OFF = 1 and no turn on event is present, the device stops at the QPU_Off state,

and waits until a valid turn on event is present.

In this state, if VDDIO supply is provided externally, the device is able to communicate

through I

C to access and modify the mirror registers in order to operate the device in

TBB mode or to program the OTP registers as described in Section 17 "OTP/TBB and

default configurations".

By default, the coin cell charger is disabled during the QPU_Off state when VIN crosses

the UVDET threshold, but it may be turned on or off in this state once it is programmed

by COINCHG_OFF during the system-on states.

If a power up event is started and any of the TRIM_NOK, OTP_NOK or STEST_NOK

flags are asserted, the device ignores the power up event and remains in the QPU_Off

state. See Section 17 "OTP/TBB and default configurations" for more details on

debugging a fuse loading failure.

Upon a power up event, the default configuration from OTP or hardwire is loaded into

their corresponding I

C functional register in the transition from QPU_Off to power up

state.

13.1.5 Power up sequence

During the power up sequence, the external regulators are turned on in a predefined

order as programmed by the default (OTP or hardwire) sequence.

If PGOOD is used as a GPO, it can also be set high as part of the power up sequence in

order to allow sequencing of any external supply/device controlled by the PGOOD pin.

The RESETBMCU is also programmed as part of the power up sequence, and it is used

as the condition to enter system-on states. The RESETBMCU may be released in the

middle of the power up sequence, in this case, the remaining supplies in the power up

continues to power up as the device is in the run state. See Section 14.5.2 "Power up

sequencing" for details.

13.1.6 System-on states

During the system-on states, the MCU is powered and out of reset and the system is fully

operational.

The system on is a virtual state composed by two modes of operations:

• Run state

• Standby state

other miscellaneous functions can be written to or read from the functional I

C register

map during the system-on states.

13.1.6.1 Run state

If the power up state is successfully completed, the state machine transitions to the run

state. In this state, RESETBMCU is released high, and the MCU is expected to boot up

and set up specific registers on the PMIC as required during the system boot up process.

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Product data sheet Rev. 11 — 24 February 2021

18 / 133

The run mode is intended to be used as the normal mode of operation for the system.

Each regulator has specific registers to control its output voltage, operation mode and/or

enable/disable state during the run state.

By default, the VSWx_RUN[7:0] / VLDOx_RUN[3:0] registers are loaded with the data

stored in the OTP_VSWx[7:0] or OTP_VLDOx[3:0] bits respectively.

SW7 uses only one global register to configure the output voltage during run or

standby mode. Upon power up the VSW7[4:0] bits are loaded with the values of the

OTP_VSW7[4:0].

Upon power up, if the switching regulator is part of the power up sequence, the

SWx_RUN_MODE[1:0] bits will be loaded as needed by the system:

• When OTP_SYNCIN_EN = 1, default SWx_RUN_MODE at power up is always set to

PWM (0b01)

• When OTP_SYNCOUT_EN = 1, default SWx_RUN_MODE at power up is always set

to PWM (0b01)

• When OTP_FSS_EN = 1, default SWx_RUN_MODE at power up shall always set to

PWM (0b01)

• If none of the above conditions are met, the default value of the SWx_RUN_MODE bits

at power up will be set by the OTP_SW_MODE bits.

When OTP_SW_MODE = 0, the default value of the SWx_RUN_MODE bits are set to

0b11 (autoskip).

When OTP_SW_MODE = 1, the default value of the SWx_RUN_MODE bits are set to

0b01 (PWM).

If the switching regulator is not part of the power up sequence, the

SWx_RUN_MODE[1:0] bits are loaded with 0b00 (OFF mode).

Likewise, if the LDO is part of the power up sequence, the LDOx_RUN_EN bit is set to

1 (enabled) by default. If the LDO is not selected as part of the power up sequence, the

LDOx_RUN_EN bit is set to 0 (disabled) by default.

In a typical system, each time the processor boots up (PMIC transitions from off mode

to run state), all output voltage configurations are reset to the default OTP configuration,

and the MCU should configure the PMIC to its desired usage in the application.

13.1.6.2 Standby state

The standby state is intended to be used as a low power (state retention) mode of

operation. In this state, the voltage regulators can be preset to a specific low power

configuration in order to reduce the power consumption during system’s sleep or state

retention modes of operations.

The standby state is entered when the STANDBY pin is pulled high or low as defined

by the STANBYINV bit. The STANDBY pin is pulled high/low by the MCU to enter/exit

system low power mode. See Section 14.9.2 "STANDBY" for detailed configuration of the

STANDBY pin.

Each regulator has specific registers to control its output voltage, operation mode and/or

enable/disable state during the standby state.

By default, the VSWx_STBY[7:0] / VLDOx_STBY[3:0] registers are loaded with the data

stored in the OTP_VSWx[7:0] or OTP_VLDOx[3:0] bits respectively.

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Product data sheet Rev. 11 — 24 February 2021

19 / 133

Upon power up, if the switching regulator is part of the power up sequence, the

SWx_STBY_MODE[1:0] bits will be loaded as needed by the system:

• When OTP_SYNCIN_EN = 1, default SWx_STBY_MODE at power up is always set to

PWM (0b01)

• When OTP_SYNCOUT_EN = 1, default SWx_STBY_MODE at power up is always set

to PWM (0b01)

• When OTP_FSS_EN = 1, default SWx_STBY_MODE at power up shall always set to

PWM (0b01)

• If none of the conditions above are met, the default value of the SWx_STBY_MODE

bits at power up will be set by the OTP_SW_MODE bits.

When OTP_SW_MODE = 0, the default value of the SWx_STBY_MODE bits are set to

0b11 (autoskip).

When OTP_SW_MODE = 1, the default value of the SWx_STBY_MODE bits are set to

0b01 (PWM).

If the switching regulator is not part of the power up sequence, the

SWx_STBY_MODE[1:0] bits are loaded with 0b00 (OFF mode).

Likewise, if the LDO is part of the power up sequence, the LDOx_RUN_EN bit is set to

1 (enabled) by default. If the LDO is not selected as part of the power up sequence, the

LDOx_RUN_EN bit is set to 0 (disabled) by default.

Upon power up, the standby registers are loaded with the same default OTP values as

the run mode. The MCU is expected to program the desired standby values during boot

up.

If any of the external regulators are disabled in the standby state, the power down

sequencer is engaged as described in Section 14.6.2 "Power down sequencing".

13.1.7 WD_Reset

When a hard watchdog reset is present, the state machine increments the

WD_EVENT_CNT[3:0] register and compares against the WD_MAX_CNT[3:0] register.

If WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0], the state machine detects a cyclic

watchdog failure, it powers down the external regulators and proceeds to the fail-safe

transition.

If WD_EVENT_CNT[3:0] < WD_MAX_CNT[3:0], the state machine performs a hard WD

reset.

A hard WD reset can be generated from either a transition in the WDI pin or a WD event

initiated by the internal watchdog counter as described in Section 15.11.2 "Watchdog

reset behaviors".

13.1.8 Power down state

During power down state, all regulators except VSNVS are disabled as configured in

the power down sequence. The power down sequence is programmable as defined in

Section 14.6.2 "Power down sequencing".

Two types of events may lead to the power down sequence:

• Non faulty turn off events: move directly into LP_Off state as soon as power down

sequence is finalized

NXP Semiconductors

PF8100; PF8200

12-channel power management integrated circuit for high performance applications

Product data sheet Rev. 11 — 24 February 2021

20 / 133

• Turn off events due to a PMIC fault: move to the fail-safe transition as soon as the

power down sequence is finalized

13.1.9 Fail-safe transition

The fail-safe transition is entered if the PF8100/PF8200 initiates a turn off event due to a

PMIC fault.

If the fail-safe transition is entered, the PF8100/PF8200 provides four FAIL bits to

indicate the source of the failure:

• The PU_FAIL is set to 1 when the device shuts down due to a power up failure

• The WD_FAIL is set to 1 when the device shuts down due to a watchdog event counter

max out

• The REG_FAIL is set to 1 when the device shuts down due to a regulator failure (fault

counter maxed out or fault timer expired)

• The TSD_FAIL is set to 1 when the device shuts down due to a thermal shutdown

The value of the FAIL bits is retained as long as VIN > UVDET.

The MCU can read the FAIL bits during the system-on states in order to obtain

information about the previous failure and can clear them by writing a 1 to them, provided

the state machine is able to power up successfully after such failure.

In PF8200, when the state machine enters the fail-safe transition, a fail-safe counter is

compared and increased, if the FS_CNT[3:0] reaches the maximum count, the device

can be programmed to move directly to the fail-safe state to prevent a cyclic failure from

happening.

13.1.10 Fail-safe state (PF8200 only)

The fail-safe state works as a safety lock-down upon a critical device/system failure. It is

reached when the FS_CNT [3:0] = FS_MAX_CNT [3:0].

A bit is provided to enable or disable the device to enter the fail-safe state upon a cyclic

failure. When the OTP_FS_BYPASS = 1, the fail-safe bypass operation is enabled and

the device always move to the LP_Off state, regardless of the value of the FS_CNT[3:0].

If the OTP_FS_BYPASS = 0, the fail-safe bypass is disabled, and the device moves to

the fail-safe state when the proper condition is met.

The maximum number of times the device can pass through the fail-safe

transition continuously prior to moving to a fail state is programmed by the

OTP_FS_MAX_CNT[3:0] bits. If the FS_MAX_CNT[3:0] = 0x00, the device moves into

the fail-safe state as soon as it fails for the very first time.

If the FSOB pin is programmed to assert upon a specific fault, the FSOB pin remains

asserted low during the fail-safe state if the corresponding fault is present when PF8200

reaches the fail-safe state.

The device can exit the fail-safe state only after a power cycle (VIN crossing UVDET)

event is present.

To avoid reaching the fail-safe state due to isolated fail-safe transition events,

the FS_CNT [3:0] is gradually decreased based on a fail-safe OK timer. The

OTP_FS_OK_TIME[2:0] bits select the default time configuration for the fail-safe OK

timer between 1 to 60 min.

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