TI MSP430FR5969-SP：抗辐射加固与超低功耗微控制器

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TI-MSP430FR5969-SP是一款高度集成的抗辐射加固型微控制器，专为工业级应用设计，特别是在对电磁兼容性和可靠性有高要求的环境中。该设备的主要特点包括： 1. **抗辐射特性**： - 设备能够工作在宽温范围(-55°C至105°C)，具备单粒子闩锁(SEL)功能，提供在125°C下高达72 MeV.cm²/mg的抗扰度，适用于高辐射环境。 - 已经通过了50krad的辐射批次验收测试，确保了设备的耐用性。 2. **嵌入式微控制器**： - 基于16位RISC架构，支持高达16MHz的时钟频率，提供高性能处理能力。 - 具有宽电源电压范围，从1.8V至3.6V，适应不同应用的需求。 3. **低功耗模式**： - 提供多种低功耗工作模式，如工作模式下约100 µA/MHz，待机(LPM3)仅消耗0.4 µA（典型值），实时时钟(LPM3.5)降低到0.25 µA，关断模式(LPM4.5)最低至0.02 µA，适合电池供电的设备。 4. **超低功耗非易失性存储**： - 配备64KB的铁电RAM(FRAM)，内存是非易失性的，且具有超低功耗写入能力，125ns的写入速度使得大量数据存储高效快速。 - 存储结构统一，支持程序、数据和存储在一个单一空间内，具有出色的写入周期持久性和抗辐射及非磁性特性。 5. **智能数字外设**： - 包含32位硬件乘法器(MPY)和3通道内部直接内存访问(DMA)，提升计算性能和数据传输效率。 - 内置日历功能，便于时间管理和任务调度。 6. **产品特性增强**： - 扩展的工作温度范围、较长的产品变更通知周期以及加强的产品生命周期管理，确保了长期的可靠性和稳定性。 - 单受控基线设计和增强的产品可追溯性，提高了质量控制水平。 TI-MSP430FR5969-SP是一款高性能、低功耗、抗辐射的嵌入式微控制器，适用于严苛的电磁环境，特别适合于航空航天、军事、医疗和其他需要长时间运行且对辐射敏感的应用场景。

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(1) For other module currents not listed here, see the module specific parameter sections.

4.9 Typical Characteristics, Current Consumption per Module

(1)

MODULE TEST CONDITIONS REFERENCE CLOCK MIN TYP MAX UNIT

Timer_A Module input clock 3 μA/MHz

Timer_B Module input clock 5 μA/MHz

eUSCI_A UART mode Module input clock 5.5 μA/MHz

eUSCI_A SPI mode Module input clock 3.5 μA/MHz

eUSCI_B SPI mode Module input clock 3.5 μA/MHz

eUSCI_B I

C mode, 100 kbaud Module input clock 3.5 μA/MHz

RTC_B 32 kHz 100 nA

MPY Only from start to end of operation MCLK 25 μA/MHz

AES Only from start to end of operation MCLK 21 μA/MHz

CRC Only from start to end of operation MCLK 2.5 μA/MHz

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

4.10 Thermal Resistance Characteristics

THERMAL METRIC PACKAGE VALUE UNIT

Junction-to-ambient thermal resistance

(1)

QFN-48 (RGZ)

30.6 °C/W

JC(TOP)

Junction-to-case (top) thermal resistance

(2)

17.2 °C/W

Junction-to-board thermal resistance

(3)

7.2 °C/W

Junction-to-board thermal characterization parameter 7.2 °C/W

Junction-to-top thermal characterization parameter 0.2 °C/W

JC(BOTTOM)

Junction-to-case (bottom) thermal resistance

(4)

1.2 °C/W

Junction-to-ambient thermal resistance, still air

(1)

QFP-48 (PHP)

26.9 °C/W

JC(TOP)

\ Junction-to-case (top) thermal resistance

(2)

16.4 °C/W

Junction-to-board thermal resistance

(3)

7.6 °C/W

Junction-to-board thermal characterization parameter 7.6 °C/W

Junction-to-top thermal characterization parameter 0.2 °C/W

JC(BOTTOM)

Junction-to-case (bottom) thermal resistance

(4)

1.5 °C/W

0.5

1.5

1 10 100 1000 10000 100000

Brownout Power-Down Level (V)

Supply Voltage Power-Down Slope (V/s)

VCC_BOR-

for reliable

device start-up

Process-Temperature Corner Case 1

Typical

Process-Temperature Corner Case 2

MIN Limit

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4.11 Timing and Switching Characteristics

4.11.1 Power Supply Sequencing

TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,

power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the

limits specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the

device including erroneous writes to RAM and FRAM.

At power up, the device does not start executing code before the supply voltage reaches V

SVSH+

if the

supply rises monotonically to this level.

Table 4-1 lists the reset power ramp requirements.

(1) In case of a supply voltage brownout, the device supply voltages need to ramp down to the specified brownout power-down level

VCC_BOR-

before the voltage is ramped up again to ensure a reliable device start-up and performance according to the data sheet

including the correct operation of the on-chip SVS module.

(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR

resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for

capacitor C

DVCC

should limit the slopes accordingly.

(3) The brownout levels are measured with a slowly changing supply. With faster slopes the MIN level required to reset the device properly

can decrease to 0 V. Use the graph in Figure 4-3 to estimate the V

VCC_BOR-

level based on the down slope of the supply voltage. After

removing VCC the down slope can be estimated based on the current consumption and the capacitance on DVCC: dV/dt = I/C with

dV/dt: slope, I: current, C: capacitance.

(4) The brownout levels are measured with a slowly changing supply.

Table 4-1. Brownout and Device Reset Power Ramp Requirements

over recommended ranges of supply voltage and operating temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCC_BOR–

Brownout power-down level

(1)(2)

| dDV

| < 3 V/s

(3)

0.7 1.68 V

| dDV

| > 300 V/s

(3)

0 V

VCC_BOR+

Brownout power-up level

(2)

| dDV

| < 3 V/s

(4)

0.79 1.74 V

Figure 4-3. Brownout Power-Down Level vs Supply Voltage Down Slope

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4.11.3 Clock Specifications

Table 4-4 lists the characteristics of the LFXT.

(1) To improve EMI on the LFXT oscillator, observe the following guidelines.

• Keep the trace between the device and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins LFXIN and LFXOUT.

• Avoid running PCB traces underneath or adjacent to the LFXIN and LFXOUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator LFXIN and LFXOUT pins.

• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DC

LFXT, SW

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the

LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following

guidelines, but should be evaluated based on the actual crystal selected for the application:

• For LFXTDRIVE = {0}, C

L,eff

= 3.7 pF.

• For LFXTDRIVE = {1}, C

L,eff

= 6 pF

• For LFXTDRIVE = {2}, 6 pF ≤ C

L,eff

≤ 9 pF

• For LFXTDRIVE = {3}, 9 pF ≤ C

L,eff

≤ 12.5 pF

(5) This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and

package capacitance. The effective load capacitance, C

L,eff

can be computed as C

× C

OUT

/ (C

+ C

OUT

), where C

and C

OUT

are the

total capacitance at the LFXIN and LFXOUT terminals, respectively.

(6) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended

effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12.5 pF. Maximum shunt capacitance of 1.6 pF. The PCB adds

additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance

of the selected crystal is met.

Table 4-4. Low-Frequency Crystal Oscillator, LFXT

(1)

over recommended ranges of supply voltage and operating temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

MIN TYP MAX UNIT

VCC.LFXT

Current consumption

OSC

= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {0},

= 25°C, C

L,eff

= 3.7 pF, ESR ≈ 44 kΩ

3.0 V 180

OSC

= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {1},

= 25°C, C

L,eff

= 6 pF, ESR ≈ 40 kΩ

3.0 V 185

OSC

= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {2},

= 25°C, C

L,eff

= 9 pF, ESR ≈ 40 kΩ

3.0 V 225

OSC

= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

= 25°C, C

L,eff

= 12.5 pF, ESR ≈ 40 kΩ

3.0 V 330

LFXT

LFXT oscillator crystal frequency LFXTBYPASS = 0 32768 Hz

LFXT

LFXT oscillator duty cycle

Measured at ACLK,

LFXT

= 32768 Hz

30% 70%

LFXT,SW

LFXT oscillator logic-level

square-wave input frequency

LFXTBYPASS = 1

(2) (3)

10.5 32.768 50 kHz

LFXT, SW

LFXT oscillator logic-level

square-wave input duty cycle

LFXTBYPASS = 1 30% 70%

LFXT

Oscillation allowance for

LF crystals

(4)

LFXTBYPASS = 0, LFXTDRIVE = {1},

LFXT

= 32768 Hz, C

L,eff

= 6 pF

210

kΩ

LFXTBYPASS = 0, LFXTDRIVE = {3},

LFXT

= 32768 Hz, C

L,eff

= 12.5 pF

300

LFXIN

Integrated load capacitance at

LFXIN terminal

(5) (6)

2 pF

LFXOUT

Integrated load capacitance at

LFXOUT terminal

(5) (6)

2 pF

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Table 4-4. Low-Frequency Crystal Oscillator, LFXT

(1)

(continued)

over recommended ranges of supply voltage and operating temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

MIN TYP MAX UNIT

(7) Includes start-up counter of 1024 clock cycles.

(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the

flag. A static condition or stuck at fault condition sets the flag.

(9) Measured with logic-level input frequency but also applies to operation with crystals.

START,LFXT

Start-up time

(7)

OSC

= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {0},

= 25°C, C

L,eff

= 3.7 pF

3.0 V 800

OSC

= 32768 Hz,

LFXTBYPASS = 0, LFXTDRIVE = {3},

= 25°C, C

L,eff

= 12.5 pF

3.0 V 1000

Fault,LFXT

Oscillator fault frequency

(8) (9)

0 3500 Hz

Table 4-5 lists the characteristics of the HFXT.

(1) To improve EMI on the HFXT oscillator, observe the following guidelines.

• Keep the traces between the device and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins HFXIN and HFXOUT.

• Avoid running PCB traces underneath or adjacent to the HFXIN and HFXOUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator HFXIN and HFXOUT pins.

• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

(2) HFFREQ = {0} is not supported for HFXT crystal mode of operation.

(3) Maximum frequency of operation of the entire device cannot be exceeded.

(4) When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics

defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DC

HFXT, SW

Table 4-5. High-Frequency Crystal Oscillator, HFXT

(1)

over recommended ranges of supply voltage and operating temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

MIN TYP MAX UNIT

DVCC.HFXT

HFXT oscillator

crystal current HF

mode at typical

ESR

OSC

= 4 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 0, HFFREQ = 1

(2)

= 25°C, C

L,eff

= 18 pF, Typical ESR, C

shunt

3.0 V

μA

OSC

= 8 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 1, HFFREQ = 1,

= 25°C, C

L,eff

= 18 pF, Typical ESR, C

shunt

120

OSC

= 16 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 2, HFFREQ = 2,

= 25°C, C

L,eff

= 18 pF, Typical ESR, C

shunt

190

OSC

= 24 MHz,

HFXTBYPASS = 0, HFXTDRIVE = 3, HFFREQ = 3,

= 25°C, C

L,eff

= 18 pF, Typical ESR, C

shunt

250

HFXT

HFXT oscillator

crystal frequency,

crystal mode

HFXTBYPASS = 0, HFFREQ = 1

(2)(3)

4 8

MHzHFXTBYPASS = 0, HFFREQ = 2

(3)

8.01 16

HFXTBYPASS = 0, HFFREQ = 3

(3)

16.01 24

HFXT

HFXT oscillator

duty cycle

Measured at SMCLK, f

HFXT

= 16 MHz 40% 50% 60%

HFXT,SW

HFXT oscillator

logic-level square-

wave input

frequency, bypass

mode

HFXTBYPASS = 1, HFFREQ = 0

(4)(3)

0.9 4

MHz

HFXTBYPASS = 1, HFFREQ = 1

(4)(3)

4.01 8

HFXTBYPASS = 1, HFFREQ = 2

(4)(3)

8.01 16

HFXTBYPASS = 1, HFFREQ = 3

(4)(3)

16.01 24

HFXT, SW

HFXT oscillator

logic-level square-

wave input duty

cycle

HFXTBYPASS = 1 40% 60%

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