2018年IEEE VHDL混合信号与模拟扩展标准发布

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2018年最新版的IEEE Standard VHDL Analog and Mixed-Signal Extensions是IEEE 1076.1语言的一个扩展，于2018年1月26日发布。该标准由设计自动化标准委员会（Design Automation Standards Committee, DAC）的IEEE Computer Society支持，旨在为混合信号和混合技术系统的描述和仿真提供全面的功能。它修订了之前的IEEE Std 1076.1-2007标准，并在2017年9月28日得到了IEEE Systems and Applications Area Board（IEEE-SA Board）的批准。 IEEE Std 1076.1™-2017规定了如何在VHDL语言中处理模拟和混合信号设计，这对于电子设计自动化（EDA）行业至关重要。它涵盖了模拟电路设计的建模、信号流控制、噪声分析、电源管理、时序行为以及与数字电路的交互等关键领域。标准允许用户利用VHDL的结构化编程模型来描述复杂系统中的连续信号行为，同时保持设计的可验证性和一致性。该标准的授权使用有限，如TUFTS大学在2018年2月19日下载时所受的限制所示，可能包括版权和使用条款。所有权利归IEEE所有，且在美国专利商标局注册为IEEE商标。该标准的出版日期为2018年1月26日，印制于美国。 VHDL Analog and Mixed-Signal Extensions部分扩展了基本的VHDL语言特性，使得设计师能够更好地模拟和验证混合信号系统中的行为，例如，通过引入模拟信号类型、模拟算术运算、滤波器模型、以及对模拟电路参数化和行为建模的支持。此外，它还定义了如何在硬件描述语言中处理噪声和电源完整性问题，这些都是现代电子产品设计中的核心挑战。总结来说，2018年IEEE Standard VHDL Analog and Mixed-Signal Extensions是电子设计工程师的重要参考资料，它增强了VHDL的适用性，促进了混合信号设计的标准化和模块化，从而提高整个行业的设计效率和产品质量。

IEEE Std 1076.1-2017

IEEE Standard VHDL Analog and Mixed-Signal Extensions

IEEE Standard VHDL Analog and

Mixed-Signal Extensions

1. Overview

1.1 Scope

This standard defines the IEEE 1076.1™ language, a hardware description language for the description and

the simulation of analog, digital, and mixed-signal systems. Informally called VHDL-AMS (VHSIC

Hardware Description Language for Analog and Mixed-Signal, where VHSIC stands for Very High Speed

Integrated Circuits), the language is built on the IEEE 1076™ (VHDL) language and extends it to provide

capabilities of writing and simulating analog and mixed-signal models.

1.2 Purpose

To support the design and verification of complex electronic systems containing a mixture of analog and

digital devices, the IEEE 1076.1 language provides, as an extension of the IEEE VHDL 1076 language, a

comprehensive set of capabilities for the description and simulation of mixed-signal and mixed-technology

systems.

The revision adds selected new features to the language definition of IEEE Std 1076.1-2007, and it updates

that standard to reflect changes in the VHDL specification, IEEE Std 1076-2008.

1.3 Structure and terminology of this standard

1.3.1 General

This document contains the complete reference of the IEEE 1076.1 VHDL language, including the

unchanged portions of the base language and the extensions. Formally, IEEE Std 1076.1-2017 defines the

extensions only, consisting of additions to, and changes of, the text of IEEE Std 1076-2008. The

corresponding text is highlighted in light gray. Text that is not highlighted is identical in this document and

in IEEE Std 1076-2008.

This standard is organized into clauses, each of which focuses on some particular area of the language.

Within each clause, individual constructs or concepts are discussed in each subclause.

Information on references can be found in Clause 2.

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IEEE Std 1076.1-2017

IEEE Standard VHDL Analog and Mixed-Signal Extensions

Each subclause describing a specific construct begins with an introductory paragraph. Next, the syntax of

the construct is described using one or more grammatical productions.

A set of paragraphs describing the meaning and restrictions of the construct in narrative form then follow.

In this document, the word shall is used to indicate a mandatory requirement. The word should is used to

indicate a recommendation. The word may is used to indicate a permissible action. The word can is used for

statements of possibility and capability.

Finally, each clause may end with examples, notes, and references to other pertinent clauses.

1.3.2 Syntactic description

The form of a VHDL description is described by means of context-free syntax using a simple variant of the

Backus-Naur form (BNF); in particular:

a) Lowercase words in roman font, some containing embedded underlines, are used to denote syntactic

categories, for example:

formal_port_list

Whenever the name of a syntactic category is used, apart from the syntax rules themselves, spaces

take the place of underlines [thus, “formal port list” would appear in the narrative description when

referring to the syntactic category in item a)].

b) Boldface words are used to denote reserved words, for example:

array

Reserved words shall be used only in those places indicated by the syntax.

c) A production consists of a left-hand side, the symbol “::=” (which is read as “can be replaced by”),

and a right-hand side. The left-hand side of a production is always a syntactic category; the

right-hand side is a replacement rule. The meaning of a production is a textual-replacement rule: any

occurrence of the left-hand side may be replaced by an instance of the right-hand side.

d) A vertical bar (|) separates alternative items on the right-hand side of a production unless it occurs

immediately after an opening brace, in which case it stands for itself, as follows:

letter_or_digit ::= letter | digit

choices ::= choice { | choice }

In the first instance, an occurrence of “letter_or_digit” can be replaced by either “letter” or “digit.”

In the second case, “choices” can be replaced by a list of “choice,” separated by vertical bars [see

item f) for the meaning of braces].

e) Square brackets [ ] enclose optional items on the right-hand side of a production; thus, the following

two productions are equivalent:

return_statement ::= return [ expression ] ;

return_statement ::= return ; | return expression ;

Note, however, that the initial and terminal square brackets in the right-hand side of the production

for signatures (see 4.5.3) are part of the syntax of signatures and do not indicate that the entire

right-hand side is optional.

f) Braces { } enclose a repeated item or items on the right-hand side of a production. The items may

appear zero or more times; the repetitions occur from left to right as with an equivalent left-recursive

rule. Thus, the following two productions are equivalent:

term ::= factor { multiplying_operator factor }

term ::= factor | term multiplying_operator factor

g) If the name of any syntactic category starts with an italicized part, it is equivalent to the category

name without the italicized part. The italicized part is intended to convey some semantic

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IEEE Std 1076.1-2017

IEEE Standard VHDL Analog and Mixed-Signal Extensions

information. For example, type_name and subtype_name are both syntactically equivalent to name

alone.

h) The term simple_name is used for any occurrence of an identifier that already denotes some

declared entity.

1.3.3 Semantic description

The meaning and restrictions of a particular construct are described with a set of narrative rules immediately

following the syntactic productions. In these rules, an italicized term indicates the definition of that term,

and identifiers appearing entirely in uppercase letters refer to definitions in package STANDARD (see

16.3).

The following terms are used in these semantic descriptions with the following meanings:

erroneous: The condition described represents an ill-formed description; however, implementations are not

required to detect and report this condition. Conditions are deemed erroneous only when it is impossible in

general to detect the condition during the processing of the language.

error: The condition described represents an ill-formed description; implementations are required to detect

the condition and report an error to the user of the tool.

illegal: A synonym for “error.”

legal: The condition described represents a well-formed description.

1.3.4 Front matter, examples, notes, references, and annexes

Prior to this subclause are several pieces of introductory material; following Clause 24 are some annexes and

an index. The front matter, annexes (except Annex B), and index serve to orient and otherwise aid the user

of this standard, but are not part of the definition of VHDL; Annex B, however, is normative.

Some clauses of this standard contain examples, notes, and cross-references to other clauses of the standard;

these parts always appear at the end of a clause. Examples are meant to illustrate the possible forms of the

construct described. Illegal examples are italicized. Notes are meant to emphasize consequences of the rules

described in the clause or elsewhere. In order to distinguish notes from the other narrative portions of this

standard, notes are set as enumerated paragraphs in a font smaller than the rest of the text. Cross-references

are meant to guide the user to other relevant clauses of the standard. Examples, notes, and cross-references

are not part of the definition of the language.

1.3.5 Incorporation of Property Specification Language

VHDL incorporates the simple subset of the Property Specification Language (PSL) as an embedded

language for formal specification of the behavior of a VHDL description. PSL is defined by

IEEE Std 1850™-2005. All PSL constructs that appear in a VHDL description shall conform to the VHDL

flavor of PSL. Within this standard, reference is made to syntactic rules of PSL. Each such reference has the

italicized prefix PSL_ and corresponds to the syntax rule in IEEE Std 1850-2005 with the same name but

without the prefix.

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IEEE Std 1076.1-2017

IEEE Standard VHDL Analog and Mixed-Signal Extensions

2. Normative references

The following referenced documents are indispensable for the application of this document (i.e., they must

be understood and used, so each referenced document is cited in text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of

the referenced document (including any amendments or corrigenda) applies.

IEEE Std 754™-1985 (Reaff 1990), IEEE Standard for Binary Floating-Point Arithmetic.

2, 3

IEEE Std 854™-1987 (Reaff 1994), IEEE Standard for Radix-Independent Floating-Point Arithmetic.

IEEE Std 1076™-2008, IEEE Standard VHDL Language Reference Manual.

IEEE Std 1850™-2005, IEEE Standard for Property Specification Language (PSL).

IEEE/ASTM SI 10™, American National Standard for Metric Practice.

ISO/IEC 8859-1:1998, Information technology—8-bit single-byte coded graphic character sets—Part 1:

Latin alphabet No. 1.

ISO/IEC 9899:1999, Programming Languages—C.

ISO/IEC 9899:1999/Cor 1:2001, Programming languages—C, Technical Corrigendum 1.

ISO/IEC 9899:1999/Cor 2:2004, Programming languages—C, Technical Corrigendum 2.

ISO/IEC 19501:2005, Information technology—Open Distributed Processing—Unified Modeling Language

(UML) Version 1.4.2.

IEEE publications are available from The Institute of Electrical and Electronics Engineers (http://standards.ieee.org/).

The IEEE standards or products referred to in this clause are trademarks of The Institute of Electrical and Electronics Engineers, Inc.

ASTM publications are available from the American Society for Testing and Materials (http://www.astm.org/).

ISO/IEC publications are available from the ISO Central Secretariat (http://www.iso.org/). ISO publications are also available in the

United States from the American National Standards Institute (http://www.ansi.org/).

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IEEE Std 1076.1-2017

IEEE Standard VHDL Analog and Mixed-Signal Extensions

3. Design entities and configurations

3.1 General

The design entity is the primary hardware abstraction in VHDL. It represents a portion of a hardware design

that has well-defined inputs and outputs and performs a well-defined function. A design entity may

represent an entire system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of abstraction

in-between. A configuration can be used to describe how design entities are put together to form a complete

design.

A design entity may be described in terms of a hierarchy of blocks, each of which represents a portion of the

whole design. The top-level block in such a hierarchy is the design entity itself; such a block is an external

block that resides in a library and may be used as a component of other designs. Nested blocks in the

hierarchy are internal blocks, defined by block statements (see 11.2).

A design entity may also be described in terms of interconnected components. Each component of a design

entity may be bound to a lower-level design entity in order to define the structure or behavior of that

component. Successive decomposition of a design entity into components, and binding those components to

other design entities that may be decomposed in like manner, results in a hierarchy of design entities

representing a complete design. Such a collection of design entities is called a design hierarchy. The

bindings necessary to identify a design hierarchy can be specified in a configuration of the top-level entity in

the hierarchy.

This clause describes the way in which design entities and configurations are defined. A design entity is

defined by an entity declaration together with a corresponding architecture body. A configuration is defined

by a configuration declaration.

3.2 Entity declarations

3.2.1 General

An entity declaration defines the interface between a given design entity and the environment in which it is

used. It may also specify declarations and statements that are part of the design entity. A given entity

declaration may be shared by many design entities, each of which has a different architecture. Thus, an

entity declaration can potentially represent a class of design entities, each with the same interface.

entity_declaration ::=

entity identifier is

entity_header

entity_declarative_part

[ begin

entity_statement_part ]

end [ entity ] [ entity_simple_name ] ;

The entity header and entity declarative part consist of declarative items that pertain to each design entity

whose interface is defined by the entity declaration. The entity statement part, if present, consists of

concurrent statements that are present in each such design entity.

If a simple name appears at the end of an entity declaration, it shall repeat the identifier of the entity

declaration.

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2018年IEEE VHDL混合信号与模拟扩展标准发布

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