FM25V20A：2Mbit SPI F-RAM存储器详解

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FM25V20A是一款由Cypress Semiconductor Corporation制造的高级存储解决方案，它是一款2-Mbit（256K x 8位）的串行（SPI）铁电随机存取存储器（F-RAM）。这款独特的非易失性内存技术在数据存储和持久性方面具有显著优势。首先，FM25V20A的特点在于其高耐用性，能够承受高达100万亿次（10^14）的读写操作，这使得它在需要频繁访问的应用场景中表现出色。数据保留时间长达151年，确保了长期存储的可靠性。它的写入过程采用NoDelay™技术，能够在快速通信中实现高效的数据更新，对于实时数据处理非常有用。作为一款SPI接口芯片，FM25V20A支持高达40 MHz的频率，这意味着它可以与各种高速电子设备无缝集成，提供了直接替换传统串行闪存和EEPROM的可能，同时支持SPI模式0 (0,0)和模式3 (1,1)，增加了灵活性。安全性是FM25V20A的另一个关键特性。它采用了先进的硬件保护机制，通过WriteProtect (WP)引脚来锁定写入操作，防止意外更改。此外，还提供软件保护手段，如WriteDisable指令，以及更精细的软件块保护，可以按数组的1/4、1/2或整个区域进行控制。在功耗方面，FM25V20A设计精良，拥有低功耗性能。在1 MHz工作频率下，主动工作状态下的电流仅为300 μA，而在待机模式下，典型电流为100 μA，进入睡眠模式时更是低至3 μA，这对于电池供电设备来说是个极大的优势。该器件的工作电压范围宽广，从2.0 V到3.6 V，适应多种电源环境，而工业级别的温度范围则为-40°C至+85°C，确保了在极端条件下也能稳定运行。 FM25V20A是一款适用于需要高性能、高可靠性和低功耗应用的存储芯片，特别是在物联网(IoT)、工业自动化和嵌入式系统等领域，它的优势尤为突出。无论是在数据持久性、通信效率还是安全性上，它都展现出了卓越的性能。

FM25V20A

Document Number: 001-90261 Rev. *D Page 5 of 22

For a microcontroller that has no dedicated SPI bus, a

general-purpose port may be used. To reduce hardware

resources on the controller, it is possible to connect the two data

pins (SI, SO) together and tie off (HIGH) the HOLD

and WP pins.

Figure 4 shows such a configuration, which uses only three pins.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the

Most Significant Bit (MSB). This is valid for both address and

data transmission.

The 2-Mbit serial F-RAM requires a 3-byte address for any read

or write operation. Because the address is only 18 bits, the first

six bits, which are fed in are ignored by the device. Although

these six bits are ‘don’t care’, Cypress recommends that these

bits be set to 0s to enable seamless transition to higher memory

densities.

Serial Opcode

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

FM25V20A uses the standard opcodes for memory accesses.

Invalid Opcode

If an invalid opcode is received, the opcode is ignored and the

device ignores any additional serial data on the SI pin until the

next falling edge of CS, and the SO pin remains tristated.

Status Register

FM25V20A has an 8-bit Status Register. The bits in the Status

described in Table 3 on page 7.

SPI Modes

FM25V20A may be driven by a microcontroller with its SPI

peripheral running in either of the following two modes:

■ SPI Mode 0 (CPOL = 0, CPHA = 0)

■ SPI Mode 3 (CPOL = 1, CPHA = 1)

For both these modes, the input data is latched in on the rising

edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles is considered. The output data

is available on the falling edge of SCK.

The two SPI modes are shown in Figure 5 on page 6 and Figure

6 on page 6. The status of the clock when the bus master is not

transferring data is:

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

Figure 3. System Configuration with SPI Port

CS1

CS2

HOLD1

HOLD2

FM25V20A FM25V20A

WP1

WP2

SCK

SI SO

SCK

HOLD WP

SCK

MOSI

MISO

SPI

Microcontroller

Figure 4. System Configuration without SPI Port

FM25V20A

Microcontroller

SCK

SI SO

HOLD WP

P1.2

P1.1

P1.0

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