NOIV1SN2000A 2/3寸全球快门CMOS图像传感器详解：高分辨率与应用

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NOIV1SN2000A是一款专为高性能图像处理应用设计的VITA 2000标准接口的图像传感器。该产品以其2.3百万像素（1920x1200像素）分辨率，支持92帧每秒（fps）的全局快门模式，在机器视觉、运动监控、安全系统以及二维条码扫描等领域展现出卓越性能。 VITA 2000是一个业界标准接口，使得NOIV1SN2000A能够与其他VITA 2000兼容的设备无缝集成，便于在自动化和嵌入式系统中实现高速图像采集和处理。其4.8微米×4.8微米的像素尺寸确保了图像细节的清晰度，2/3英寸光学格式则提供了宽广的视野范围。这款传感器有两种输出模式：LVDS和CMOS，分别提供10位模拟信号数字化和8位或10位数字输出，满足不同的数据传输需求。它具有四个LVDS串行输出接口或并行CMOS输出，可以灵活配置以适应不同应用场景下的信号传输。 NOIV1SN2000A采用全局和滚筒式快门技术，提供了两种曝光模式，以应对高速运动场景下可能的图像稳定性挑战。内置的10位ADC保证了信号转换的高精度，而随机可编程区域感兴趣区（ROI）读取功能则允许用户定制感兴趣的图像区域，进一步提高处理效率。此外，传感器还具备自动曝光控制（AEC）功能，能根据环境光照变化自动调整曝光设置，确保在各种照明条件下都能获取准确的图像。供电方面，它支持双电源输入（3.3V和1.8V），具有良好的温度适应性，工作温度范围为0°C至70°C，确保在恶劣环境中也能稳定运行。封装形式包括52针LCC和裸片，以适应不同封装需求。在功耗方面，LVDS模式下，传感器最大消耗520毫瓦，而在CMOS输出模式下，功耗降低到385毫瓦，这有助于延长电池寿命或者在电源受限的环境中优化能源利用。 NOIV1SN2000A图像传感器凭借其高性能、灵活性和广泛的适用性，是工业自动化、安防监控和物联网应用的理想选择。对于那些寻求高清晰度、快速响应和精确控制的系统设计师来说，这款传感器无疑是一个不可或缺的关键组件。

NOIV1SN2000A

Rev. 2| www.onsemi.com | Page 11 of 66

Image Core

The image core consists of:

■ Pixel Array

■ Address Decoders and Row Drivers

■ Pixel Biasing

The pixel array contains 1920 (H) x 1200 (V) readable pixels with

a pixel pitch of 4.8 µm. Four dummy pixel rows and columns are

placed at every side of the pixel array to eliminate possible edge

effects. The sensor uses a 5T pixel architecture, which makes it

possible to read out the pixel array in global shutter mode with

double sampling (DS), or in rolling shutter mode with correlated

double sampling (CDS).

The function of the row drivers is to access the image array line

by line, or all lines together, to reset or read the pixel data. The

row drivers are controlled by the on-chip sequencer and can

access the pixel array in global and rolling shutter modes.

The pixel biasing block guarantees that the data on a pixel is

transferred properly to the column multiplexer when the row

drivers select a pixel line for readout.

Phase Locked Loop

The PLL accepts a (low speed) clock and generates the required

high speed clock. Optionally this PLL can be bypassed. Typical

input clock frequency is 62 MHz.

LVDS Clock Receiver

The LVDS clock receiver receives an LVDS clock signal and

distributes the required clocks to the sensor.

Typical input clock frequency is 310 MHz in 10-bit mode and

248 MHz in 8-bit mode. The clock input needs to be terminated

with a 100-

 resistor.

Column Multiplexer

All pixels of one image row are stored in the column

sample-and-hold (S/H) stages. These stages store both the reset

and integrated signal levels.

The data stored in the column S/H stages is read out through 8

parallel differential outputs operating at a frequency of 31 MHz.

At this stage, the reset signal and integrated signal values are

transferred into an FPN-corrected differential signal.

The column multiplexer also supports read-1-skip-1 and

read-2-skip-2 mode. Enabling this mode can speed up the frame

rate, with a decrease in resolution.

Bias Generator

The bias generator generates all required reference voltages

and bias currents that the on-chip blocks use. An external

resistor of 47 k, connected between pin IBIAS_MASTER and

gnd_33, is required for the bias generator to operate properly.

Analog Front End

The AFE contains 8 channels, each containing a PGA and a

10-bit ADC.

For each of the 8 channels, a pipelined 10-bit ADC is used to

convert the analog image data into a digital signal, which is

delivered to the data formatting block. A black calibration loop is

implemented to ensure that the black level is mapped to match

the correct ADC input level.

Data Formatting

The data block receives data from two ADCs and multiplexes this

data to one data stream. A cyclic redundancy check (CRC) code

is calculated on the passing data.

A frame synchronization data block is foreseen to transmit

synchronization codes such as frame start, line start, frame end,

and line end indications.

The data block calculates a CRC once per line for every channel.

This CRC code can be used for error detection at the receiving

end.

Serializer and LVDS Interface (V1-SN/SE only)

The serializer and LVDS interface block receives the formatted

(10-bit or 8-bit) data from the data formatting block. This data is

serialized and transmitted by the LVDS output driver.

In 10-bit mode, the maximum output data rate is 620 Mbps per

channel. In 8-bit mode, the maximum output data rate is 496

Mbps per channel.

In addition to the LVDS data outputs, two extra LVDS outputs are

available. One of these outputs carries the output clock, which is

skew aligned to the output data channels. The second LVDS

output contains frame format synchronization codes to serve

system-level image reconstruction.

Output MUX (V2-SN/SE only)

The output MUX multiplexes the four data channels to one

channel and transmits the data words using a 10-bit parallel

CMOS interface.

Frame synchronization information is communicated by means

of frame and line valid strobes.

Sequencer

The sequencer:

■ Controls the image core. Starts and stops integration in rolling

and global shutter modes and control pixel readout.

■ Operates the sensor in master or slave mode.

■ Applies the window settings. Organizes readouts so that only

the configured windows are read.

■ Controls the column multiplexer and analog core. Applies gain

settings and subsampling modes at the correct time, without

corrupting image data.

■ Starts up the sensor correctly when leaving standby mode.

Automatic Exposure Control

The AEC block implements a control system to modulate the

exposure of an image. Both integration time and gains are

controlled by this block to target a predefined illumination level.

NOIV1SN2000A

Rev. 2| www.onsemi.com | Page 12 of 66

Operating Modes

The VITA 2000 sensor is able to operate in the following shutter

modes:

■ Global Shutter Mode

❐ Pipelined Global Shutter

•Master

•Slave

❐ Triggered Global Shutter

•Master

•Slave

■ Rolling Shutter Mode

Global Shutter Mode

In the global shutter mode, light integration takes place on all

pixels in parallel, although subsequent readout is sequential.

Figure 8 shows the integration and readout sequence for the

synchronous shutter. All pixels are light sensitive at the same

period of time. The whole pixel core is reset simultaneously and

after the integration time all pixel values are sampled together on

the storage node inside each pixel. The pixel core is read out line

by line after integration. Note that the integration and readout can

occur in parallel or sequentially.

Figure 8. Global Shutter Operation

Pipelined Global Shutter

In pipelined global shutter mode, the integration and readout are

done in parallel. Images are continuously read and integration of

frame N is ongoing during readout of the previous frame N-1. The

readout of every frame starts with a Frame Overhead Time

(FOT), during which the analog value on the pixel diode is trans-

ferred to the pixel memory element. After the FOT, the sensor is

read out line per line and the readout of each line is preceded by

the Row Overhead Time (ROT). Figure 9 shows the exposure

and readout time line in pipelined global shutter mode.

Figure 9. Integration and Readout for Pipelined Shutter

■ Master

In this operation mode, the integration time is set through the

images autonomously. The sensor acquires images without any

user interaction.

■ Slave

The slave mode adds more manual control to the sensor. The

exposure time registers are ignored in this mode and the

integration time is controlled by an external pin. As soon as the

control pin is asserted, the pixel array goes out of reset and

integration starts. The integration continues until the external pin

is de-asserted by the system. Now, the image is sampled and the

readout is started. Figure 10 shows the relation between the

external trigger signal and the exposure/readout timing.

Line Number

Time

Integration Time

Burst

Readout

Time

Common Reset Common Sample & Hold

Reset

Exposure Time N

Reset

N+1

Exposure Time N+1

Readout Frame N-1 FOTFOT Readout Frame N FOT

Integration Time

Handling

Readout

Handling

ROT Line Readout

FOT FOT

NOIV1SN2000A

Rev. 2| www.onsemi.com | Page 13 of 66

Figure 10. Pipelined Shutter Operated in Slave Mode .

Triggered Global Shutter

In this mode, manual intervention is required to control both the

integration time and the start of readout. After the integration

time, indicated by a user controlled pin, the image core is read

out. After this sequence, the sensor goes to an idle mode until a

new user action is detected.

The three main differences with the pipelined global shutter

mode are

■ Upon user action, one single image is read.

■ Integration and readout are done sequentially. However, the

user can control the sensor in such a way that two consecutive

batches are overlapping, that is, having concurrent integration

and readout.

■ Integration and readout is under user control through an

external pin.

This mode requires manual intervention for every frame. The

pixel array is kept in reset state until requested.

The triggered global mode is also controlled in a master or slave

mode fashion.

■ Master

In this mode, a rising edge on the synchronization pin is used to

trigger the start of integration and readout. The integration time

is defined by a register setting. The sensor autonomously

integrates during this predefined time, after which the FOT starts

and the image array is readout sequentially. A falling edge on the

synchronization pin does not have any impact on the readout or

integration and subsequent frames are started again for each

rising edge. Figure 11 shows the relation between the external

trigger signal and the exposure/readout timing.

If a rising edge is applied on the external trigger before the

exposure time and FOT of the previous frame is complete, it is

ignored by the sensor.

Figure 11. Triggered Shutter Operated in Master Mode .

■ Slave

Integration time control is identical to the pipelined shutter slave

mode. An external synchronization pin controls the start of

integration. When it is de-asserted, the FOT starts. The analog

value on the pixel diode is transferred to the pixel memory

element and the image readout can start. A request for a new

frame is started when the synchronization pin is asserted again.

Reset

Exposure Tim e N

Reset

N+1

Exposure Time N+1

Readout N-1 FOTFOT Readout N FOT

Integration T im e

Handling

Readout

Handling

ROT L ine R e ad ou t

Exte rnal Trig ger

FOT FOT

Reset

Exposure Time N

Reset

N+1

Exposure Time N+1

Readout N-1 FOTFOT Readout N FOT

Integration Time

Handling

Readout

Handling

ROT Line Readout

External Trigger

No effect on falling edge

FOT FOT

NOIV1SN2000A

Rev. 2| www.onsemi.com | Page 14 of 66

Rolling Shutter Mode

Another shutter mode supported by the sensor is the rolling

shutter mode. The shutter mechanism is an electronic rolling

shutter and the sensor operates in a streaming mode similar to

a video. This mechanism is controlled by the on-chip sequencer

logic. There are two Y pointers. One points to the row that is to

be reset for rolling shutter operation, the other points to the row

to be read out. Functionally, a row is reset first and selected for

read out sometime later. The time elapsed between these two

operations is the exposure time.

Figure 12. Rolling Shutter Operation

Figure 12 schematically indicates the relative shift of the

integration times of different lines during the rolling shutter

operation. Each row is read and reset in a sequential way. Each

row in a particular frame is integrated for the same time, but all

lines in a frame 'see' a different stare time. As a consequence,

fast horizontal moving objects in the field of view give rise to

motion artifacts in the image; this is an unavoidable property of

a rolling shutter.

In rolling shutter mode, the pixel Fixed Pattern Noise (FPN) is

corrected on-chip by using the CDS technique. After light

integration on all pixels in a row is complete, the storage node in

the pixel is being reset. Afterwards the integrated signal is trans-

ferred to that pixel storage node. The difference between the

reset level and integrated signal is the FPN corrected signal. The

advantage of this technique, compared to the DS technique used

in the global shutter modes, is that the reset noise of the pixel

storage node is cancelled. This results in a lower temporal noise

level.

Sensor Operation

Flowchart

Figure 13 shows the sensor operation flowchart. The sensor can

be in six different 'states'. Every state is indicated with the oval

circle. These states are:

■ Power off

■ Low power standby

■ Standby (1)

■ Standby (2)

■ Idle

■ Running

These states are ordered by power dissipation. In 'power-off'

state, the power dissipation is minimal; in 'running' state the

power dissipation is maximal.

On the other hand, the lower the power consumption, the more

actions (and time) are required to put the sensor in 'running' state

and grab images.

This flowchart allows the trade-off between power saving and

enabling time of the sensor.

Next to the six 'states' a set of 'user actions', indicated by arrows,

are included in the flowchart. These user actions make it possible

to move from one state to another.

Sensor States

Power Off

In this state, the sensor is inactive. All power supplies are down

and the power dissipation is zero.

Low Power Standby

In low power standby state, all power supplies are on, but inter-

nally every block is disabled. No internal clock is running (PLL /

LVDS clock receiver is disabled).

All register settings are unchanged.

Only a subset of the SPI registers is active for read/write in order

to be able to configure clock settings and leave the low power

standby state. The only SPI registers that should be touched are

the ones required for the 'Enable Clock Management' action

described in Enable Clock Management- Part 1 on page 16

Standby (1)

In standby state, the PLL/LVDS clock receiver is running, but the

derived logic clock signal is not enabled.

Standby (2)

In standby state, the derived logic clock signal is running. All SPI

registers are active, meaning that all SPI registers can be

accessed for read or write operations. All other blocks are

disabled.

Idle

In the idle state, all internal blocks are enabled, except the

sequencer block. The sensor is ready to start grabbing images

as soon as the sequencer block is enabled.

Running

In running state, the sensor is enabled and grabbing images. The

sensor can be operated in different rolling/global master/slave

modes.

Line Number

Time

Integration Time Frame Time

在低电压模式下，只有一些spi寄存器能访问，就是时钟模块

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