新型高压超结器件：部分轻掺杂P柱SJ-LDMOS

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"带有部分轻掺杂柱的高压超结横向双扩散金属氧化物半导体是一种新型的功率半导体器件设计，旨在提高击穿电压和优化性能。该技术基于超结结构，结合了部分轻掺杂P柱，以实现更好的电荷平衡和电场调控，从而提升器件的耐压能力。" 在电子工程领域，超结（Super-Junction）技术是用于提升功率半导体器件，如横向双扩散金属氧化物半导体（LDMOS）性能的一种关键方法。传统的LDMOS器件在高压应用中面临电场集中和击穿电压较低的问题。超结技术通过在半导体内部创建交替的高掺杂N型和P型区域，有效地分散了电场，提高了器件的击穿电压。在这个特定的研究中，研究人员提出了一种改进的超结LDMOS结构，即部分轻掺杂P柱（PD）的SJ-LDMOS。这种设计的独特之处在于，部分P柱的轻掺杂特性使得电荷更加平衡，能有效抑制衬底辅助的耗尽效应。这种效应会导致不必要的电荷积累和电场增强，进而影响器件的稳定性。通过减少这部分电荷，器件的电场分布得到优化，有利于提高击穿电压。此外，P柱和P-型区形成的结会产生一个新的电场峰值，这进一步调节了表面电场的分布。电场的均匀化有助于防止局部过热和电击穿，从而提高器件的耐受高压能力。这一创新设计不仅提升了击穿电压（BV），而且由于采用了与常规SJ-LDMOS相似的导电路径，其比导通电阻（R-on, R-sp）保持在相近水平，这意味着在提供更高电压承受能力的同时，器件的导通损耗并未显著增加。根据仿真结果，当漂移长度为15微米时，PD SJ-LDMOS的表面横向电场平均值达到了20 V/μm，这对应于300V的击穿电压。这样的性能指标对于高压应用，如电力转换、电源管理以及射频功率放大等，具有重要的实际意义。这项研究展示了一种通过部分轻掺杂P柱优化超结LDMOS性能的新策略，该策略在不牺牲器件的导通性能的前提下，显著提升了其击穿电压，为高压功率半导体器件的设计提供了新的思路。未来的研究可能会进一步探索这种设计在不同应用条件下的表现，以及如何通过材料选择和工艺优化来进一步提升其性能。

Chin. Phys. B Vol. 22, No. 6 (2013) 068501

High-voltage super-junction lateral double-diffused metal oxide

semiconductor with a partial lightly doped pillar

∗

Wu Wei(伍伟)

†

, Zhang Bo(张波), Fang Jian(方健),

Luo Xiao-Rong(罗小蓉), and Li Zhao-Ji(李肇基)

State Key Laboratory of Electronic Thin Films and Integrated Devices,

University of Electronic Science and Technology of China, Chengdu 610054, China

(Received 13 September 2012; revised manuscript received 15 December 2012)

A novel super-junction lateral double-diffused metal–oxide semiconductor (SJ-LDMOS) with a partial lightly doped

P pillar (PD) is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses

the substrate-assisted depletion effect. Secondly, the new electric ﬁeld peak produced by the P/P

−

junction modulates the

surface electric ﬁeld distribution. Both of these result in a high breakdown voltage (BV). In addition, due to the same

conduction paths, the speciﬁc on-resistance (R

on,sp

) of the PD SJ-LDMOS is approximately identical to the conventional

SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric ﬁeld of the PD SJ-LDMOS

reaches 20 V/µm at a 15 µm drift length, resulting in a BV of 300 V.

Keywords: super-junction, lateral double-diffused metal–oxide semiconductor, partial lightly doped pillar,

electric ﬁeld modulation, breakdown voltage

PACS: 85.30.De, 85.30.Tv, 84.70.p DOI: 10.1088/1674-1056/22/6/068501

1. Introduction

With the development of smart power-integrated cir-

cuits (SPICs), the demand for power devices that can be

easily integrated into SPICs has been increasing more and

more. For a commonly used integrated device, the lateral

double-diffusion metal–oxide semiconductor ﬁeld-effect tran-

sistor (MOSFET)/(LDMOS) acts as an important constituent

in power electronics applications. The super-junction (SJ)

concept

[1]

used in the LDMOS

[2,3]

improves the tradeoff char-

acteristics between the breakdown voltage and the speciﬁc on-

resistance (R

on,sp

). Unfortunately, the N pillars of the conven-

tional SJ-LDMOST are depleted by neighboring P pillars as

well as by the P substrate, while the P pillars are depleted by

neighboring N pillars only. This is called the substrate-assisted

depletion effect. This effect causes a charge imbalance and re-

sults in the decrease of the breakdown voltage (BV). To elim-

inate it, several new structures have been reported.

[4–13]

In this paper, an SJ-LDMOS with partial lightly doped P

pillar (PD) is proposed to suppress the substrate-assisted de-

pletion effect. Owing to the decrease in the charges in the P

pillar, the charge balance is achieved and the new peak appear-

ing at the P/P

−

junction modulates the surface electric ﬁeld

distribution. Thus, a higher BV is obtained according to the

simulation results.

2. Device structure and mechanism

The proposed PD SJ-LDMOS is illustrated in Fig. 1. The

key feature of the device is that the P pillar in the SJ region is

split into two distinct parts. The ﬁrst one is the heavily doped P

pillar, of which the doping concentration is equal to that of the

N pillar. The second is the lightly doped P pillar with a doping

concentration of N

and a length L

. The cross section along

the AA

plane is shown in Fig. 2. On the one hand, the use

of the lightly doped P pillar causes a reduction in the p-type

charge density, thereby ensuring the charge balance among

the N pillar, the P pillar, and the P substrate. The substrate-

assisted depletion effect therefore can be suppressed. On the

other hand, the electric ﬁeld peak which occurs at the P/P

−

junction modulates the electric ﬁeld distribution in the N pil-

lar, which causes a uniform distribution of the surface electric

ﬁeld.

Three-dimensional (3D) device simulations are carried

out by Sentaurus

[14]

in order to demonstrate the performance

of the PD SJ-LDMOS. The PD SJ-LDMOS is compared with

the conventional SJ-LDMOS, and the relevant device parame-

ters are listed in Table 1.

P-body

source

gate

drain

P substrate (ρ

sub

)

N pillar

A’

B’

N(N

)

P(N

)

Fig. 1. Three-dimensional (3D) view of the PD SJ-LDMOS.

∗

Project supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2010ZX02201), the

National Natural Science Foundation of China (Grant No. 61176069), and the National Defense Pre-Research of China (Grant No. 51308020304).

†

Corresponding author. E-mail: wuweiwwu@163.com

068501-1

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