PCI EXPRESS 2.0 BASE SPECIFICATION, REV. 0.9
19
TABLE 7-5: SECONDARY STATUS REGISTER ............................................................................... 448
TABLE 7-6: BRIDGE CONTROL REGISTER.................................................................................... 450
TABLE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER ADDED REQUIREMENTS ............... 451
T
ABLE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER ADDED REQUIREMENTS ........ 452
T
ABLE 7-9: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................... 455
TABLE 7-10: PCI EXPRESS CAPABILITIES REGISTER................................................................... 456
TABLE 7-11: DEVICE CAPABILITIES REGISTER............................................................................ 460
TABLE 7-12: DEVICE CONTROL REGISTER.................................................................................. 464
T
ABLE 7-13: DEVICE STATUS REGISTER ..................................................................................... 471
T
ABLE 7-14: LINK CAPABILITIES REGISTER................................................................................ 473
TABLE 7-15: LINK CONTROL REGISTER ...................................................................................... 478
TABLE 7-16: LINK STATUS REGISTER ......................................................................................... 484
TABLE 7-17: SLOT CAPABILITIES REGISTER ............................................................................... 487
T
ABLE 7-18: SLOT CONTROL REGISTER...................................................................................... 490
T
ABLE 7-19: SLOT STATUS REGISTER......................................................................................... 493
TABLE 7-20: ROOT CONTROL REGISTER..................................................................................... 495
TABLE 7-21: ROOT CAPABILITIES REGISTER............................................................................... 497
TABLE 7-22: ROOT STATUS REGISTER........................................................................................ 497
TABLE 7-23: DEVICE CAPABILITIES 2 REGISTER......................................................................... 498
TABLE 7-24: DEVICE CONTROL 2 REGISTER................................................................................ 500
TABLE 7-25: LINK CONTROL 2 REGISTER ................................................................................... 502
TABLE 7-26: LINK STATUS 2 REGISTER ...................................................................................... 504
TABLE 7-27: PCI EXPRESS ENHANCED CAPABILITY HEADER..................................................... 506
TABLE 7-28: ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER......................... 509
TABLE 7-29: UNCORRECTABLE ERROR STATUS REGISTER ......................................................... 510
TABLE 7-30: UNCORRECTABLE ERROR MASK REGISTER............................................................ 511
TABLE 7-31: UNCORRECTABLE ERROR SEVERITY REGISTER ...................................................... 513
TABLE 7-32: CORRECTABLE ERROR STATUS REGISTER.............................................................. 514
TABLE 7-33: CORRECTABLE ERROR MASK REGISTER................................................................. 515
TABLE 7-34: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER.................................. 516
T
ABLE 7-35: HEADER LOG REGISTER ......................................................................................... 517
TABLE 7-36: ROOT ERROR COMMAND REGISTER ....................................................................... 518
T
ABLE 7-37: ROOT ERROR STATUS REGISTER ............................................................................ 520
T
ABLE 7-38: ERROR SOURCE IDENTIFICATION REGISTER ........................................................... 522
TABLE 7-39: VIRTUAL CHANNEL ENHANCED CAPABILITY HEADER........................................... 525
TABLE 7-40: PORT VC CAPABILITY REGISTER 1......................................................................... 526
T
ABLE 7-41: PORT VC CAPABILITY REGISTER 2......................................................................... 527
TABLE 7-42: PORT VC CONTROL REGISTER ............................................................................... 528
T
ABLE 7-43: PORT VC STATUS REGISTER .................................................................................. 529
TABLE 7-44: VC RESOURCE CAPABILITY REGISTER................................................................... 530
TABLE 7-45: VC RESOURCE CONTROL REGISTER....................................................................... 531
T
ABLE 7-46: VC RESOURCE STATUS REGISTER.......................................................................... 534
TABLE 7-47: DEFINITION OF THE 4-BIT ENTRIES IN THE VC ARBITRATION TABLE ..................... 535
T
ABLE 7-48: LENGTH OF THE VC ARBITRATION TABLE ............................................................. 535
T
ABLE 7-49: LENGTH OF PORT ARBITRATION TABLE ................................................................. 537
T
ABLE 7-50: DEVICE SERIAL NUMBER ENHANCED CAPABILITY HEADER .................................. 538