博通B50610千兆以太网集成芯片技术手册

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"B50610-DS07-RDS是博通公司的一款千兆以太网收发器手册，主要介绍了B50610芯片的功能、特性及应用场景。" 博通B50610是一款集成了1000BASE-T、100BASE-TX和10BASE-T三速千兆以太网物理层功能的单片CMOS芯片。该芯片在标准的Cat5 UTP（非屏蔽双绞线）电缆上可支持1000BASE-T、100BASE-TX和10BASE-T以太网协议，且对于10BASE-T，它还兼容Cat3、Cat4和Cat5 UTP电缆。B50610是一个高度集成的解决方案，它包括数字自适应均衡器、模数转换器（ADCs）、锁相环（PLLs）、线路驱动器、编码器、解码器、回声消除器、串扰消除器以及所有必要的辅助电路。基于博通成熟的数字信号处理技术，B50610设计符合Rapid Gigabit Media Independent Interface (RGMII)标准，这意味着它可以与业界标准的以太网媒体访问控制器（MAC）和交换机控制器无缝配合。为了确保在最恶劣的Cat5电缆条件下可靠运行，B50610具备自动协商能力，能自动识别网络速度并适应连接的设备。 B50610的关键特性包括： 1. 三速支持：1000Mbps、100Mbps和10Mbps以太网速率。 2. 自适应均衡器：用于在长距离或质量较差的电缆上补偿信号损失。 3. ADCs和PLLs：提供精确的信号处理和时钟恢复。 4. 兼容多种UTP电缆类型：增强网络部署的灵活性。 5. RGMII兼容性：与各种MAC和交换机控制器的互操作性。 6. 自动协商：根据连接设备的能力自动调整速度。在实际应用中，B50610适用于需要高带宽、低延迟和可靠连接的网络设备，如路由器、交换机、服务器和嵌入式系统中的网卡等。其高性能和高度集成的特性使其成为构建千兆以太网网络的理想选择，尤其是在考虑成本效益和空间效率时。通过这款芯片，博通提供了强大的物理层解决方案，以满足不断增长的高速网络需求。

3/9/2010 70LCX

B50610 Data Sheet

09/18/09

Broadcom Corporation

Page xvi Document B50610-DS07-R

Expansion Register 08H: 10BT Controls.............................................................................................111

Auto Early DAC Wake ..................................................................................................................111

Section 5: Timing and AC Characteristics.................................................................... 112

REFCLK Input Timing...............................................................................................................................113

Section 6: Electrical Characteristics ............................................................................. 119

Section 7: Mechanical and Thermal .............................................................................. 121

ROHS-Compliant Packaging....................................................................................................................121

Mechanical Information............................................................................................................................122

Thermal Information .................................................................................................................................124

Section 8: Ordering Information .................................................................................... 125

3/9/2010 70LCX

Data Sheet B50610

09/18/09

Broadcom Corporation

Document B50610-DS07-R Page xvii

LIST OF FIGURES

Figure 1: Functional Block Diagram....................................................................................................................i

Figure 2: Typical RGMII-to-10/100/100BASE-T Application ............................................................................. 2

Figure 3: 100-Pin FBGA Pinout Diagram, Top View....................................................................................... 18

Figure 4: B50610 48-Pin MLP Pinout Diagram, Top View.............................................................................. 19

Figure 5: Internal Loopback Mode .................................................................................................................. 23

Figure 6: Lineside (Remote) Loopback Mode................................................................................................. 24

Figure 7: External Loopback Mode ................................................................................................................. 25

Figure 8: LED Circuit for Dual Input Configuration/LED Output Pins.............................................................. 30

Figure 9: Programmable LED Multiplexer....................................................................................................... 31

Figure 10: Reset Timing.................................................................................................................................. 112

Figure 11: REFCLK Input Timing.................................................................................................................... 113

Figure 12: Management Interface Timing ....................................................................................................... 114

Figure 13: RGMII Input Timing (Normal Mode): GTXCLK and TXD[3:0] ........................................................ 115

Figure 14: RGMII Input Timing (Delayed Mode): GTXCLK and TXD[3:0] ...................................................... 116

Figure 15: RGMII Output Timing (Normal Mode): RXC and RXD[3:0]............................................................ 117

Figure 16: RGMII Output Timing (Delayed Mode): RXC and RXD[3:0] .......................................................... 118

Figure 17: 100-Pin FBGA Package................................................................................................................. 122

Figure 18: 48-Pin MLP Package ..................................................................................................................... 123

3/9/2010 70LCX

B50610 Data Sheet

09/18/09

Broadcom Corporation

Page xviii Document B50610-DS07-R

LIST OF TABLES

Table 1: Hardware Mode Selection.................................................................................................................. 1

Table 2: Hardware Signal Descriptions..........................................................................................................11

Table 3: 1000BASE-T External Loopback With External Loopback Plug ......................................................25

Table 4: 1000BASE-T External Loopback Without External Loopback Plug .................................................25

Table 5: 100BASE-TX External Loopback With External Loopback Plug ......................................................25

Table 6: 100BASE-TX External Loopback Without External Loopback Plug.................................................25

Table 7: 10BASE-TX External Loopback With External Loopback Plug ........................................................26

Table 8: 10BASE-T External Loopback Without External Loopback Plug .....................................................26

Table 9: RGMII Transmit Data .......................................................................................................................28

Table 10: RGMII Receive Data ........................................................................................................................29

Table 11: Dual Input Configuration/LED Outputs.............................................................................................30

Table 12: Programmable LEDs........................................................................................................................31

Table 13: LINKSPD[2:1] LED Function ............................................................................................................32

Table 14: 48-Pin MLP Active Pin Test Function in JTAG Mode.......................................................................32

Table 15: 48-Pin MLP PHY Address Based on PHYA[0] and TEST[3:2] Settings...........................................32

Table 16: 48-Pin MLP RGMII Mode .................................................................................................................33

Table 17: 48-Pin MLP LOM LED Link Signal Rate Reporting ..........................................................................33

Table 18: 48-Pin MLP RGMII Modes for LOM LED Operation ........................................................................33

Table 19: Using TEST[3:2] Pins to Set JTAG, Normal Operation, and PHYA Modes .....................................34

Table 20: 48-Pin MLP Package RGMII Mode Selection ..................................................................................34

Table 21: LED Modes ......................................................................................................................................36

Table 22: MII Management Frame Format ......................................................................................................39

Table 23: Register Map....................................................................................................................................40

Table 24: 1000BASE-T/100BASE-TX/10BASE-T MII Control Register (Address 00h) ...................................42

Table 25: 1000BASE-T/100BASE-TX/10BASE-T MII Status Register (Address 01h).....................................44

Table 26: 1000BASE-T/100BASE-TX/10BASE-T PHY Identifier Register (Addresses 02h and 03h).............47

Table 27: 1000BASE-T/100BASE-TX/10BASE-T Auto-Negotiation Advertisement Register (Address 04h) ..48

Table 28: 1000BASE-T/100BASE-TX/10BASE-T Auto-Negotiation Link Partner Ability Register

(Address 05h)...................................................................................................................................50

Table 29: 1000BASE-T/100BASE-TX/10BASE-T Auto-Negotiation Expansion Register (Address 06h) ........52

Table 30: 1000BASE-T/100BASE-TX/10BASE-T Next Page Transmit Register (Address 07h) .....................53

Table 31: 1000BASE-T/100BASE-TX/10BASE-T Link Partner Received Next Page Register (Address 08h) 54

Table 32: 1000BASE-T Control Register (Address 09h)..................................................................................55

3/9/2010 70LCX

Data Sheet B50610

09/18/09

Broadcom Corporation

Document B50610-DS07-R Page xix

Table 33: 1000BASE-T Status Register (Address 0Ah) .................................................................................. 56

Table 34: 1000BASE-T/100BASE-TX/10BASE-T IEEE Extended Status Register (Address 0Fh)................. 58

Table 35: 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Control Register (Address 10h) ................ 59

Table 36: 1000BASE-T/100BASE-TX/10BASE-T PHY Extended Status Register (Address 11h).................. 62

Table 37: 1000BASE-T/100BASE-TX/10BASE-T Receive Error Counter Register (Address 12h)................. 65

Table 38: 1000BASE-T/100BASE-TX/10BASE-T False Carrier Sense Counter Register (Address 13h)....... 65

Table 39: 1000BASE-T/100BASE-TX/10BASE-T Receiver NOT_OK Counter Register (Address 14h)......... 65

Table 40: 1000BASE-T/100BASE-TX/10BASE-T Expansion Register Access Register (Address 17h)......... 66

Table 41: Expansion Register Select Values................................................................................................... 66

Table 42: 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Shadow Values Access.......................... 67

Table 43: Reading Register 18h ...................................................................................................................... 67

Table 44: Writing Register 18h ........................................................................................................................ 67

Table 45: 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Control Register (Address 18h, Shadow Value

000).................................................................................................................................................. 68

Table 46: 10BASE-T Register (Address 18h, Shadow Value 001).................................................................. 70

Table 47: 1000BASE-T/100BASE-TX/10BASE-T Power/MII Control Register (Address 18h, Shadow Value

010).................................................................................................................................................. 72

Table 48: 1000BASE-T/100BASE-TX/10BASE-T Miscellaneous Test Register (Address 18h, Shadow Value

100).................................................................................................................................................. 73

Table 49: 1000BASE-T/100BASE-TX/10BASE-T Miscellaneous Control Register (Address 18h, Shadow Value

111).................................................................................................................................................. 75

Table 50: 1000BASE-T/100BASE-TX/10BASE-T Auxiliary Status Summary Register (Address 19h) ........... 77

Table 51: 1000BASE-T/100BASE-TX/10BASE-T Interrupt Status Register (Address 1Ah) ........................... 80

Table 52: 1000BASE-T/100BASE-TX/10BASE-T Interrupt Mask Register (Address 1Bh) ............................. 83

Table 53: 1000BASE-T/100BASE-TX/10BASE-T Register 1Ch Shadow Values ........................................... 84

Table 54: 1000BASE-T/100BASE-TX/10BASE-T Spare Control 1 Register (Address 1Ch, Shadow Value

00010).............................................................................................................................................. 85

Table 55: Default LED1 and LED2 Status ....................................................................................................... 86

Table 56: Linkspeed LED1 and LED2 Status .................................................................................................. 86

Table 57: 1000BASE-T/100BASE-TX/10BASE-T Clock Alignment Control Register

(Address 1Ch, Shadow Value 00011) ............................................................................................. 87

Table 58: 1000BASE-T/100BASE-TX/10BASE-T Spare Control 2 Register (Address 1Ch, Shadow Value

00100).............................................................................................................................................. 88

Table 59: 1000BASE-T/100BASE-TX/10BASE-T Spare Control 3 Register (Address 1Ch, Shadow Value

00101).............................................................................................................................................. 89

Table 60: 1000BASE-T/100BASE-TX/10BASE-T LED Status Register (Address 1Ch, Shadow Value

01000).............................................................................................................................................. 90

Table 61: 1000BASE-T/100BASE-TX/10BASE-T LED Control Register (Address 1Ch, Shadow Value

3/9/2010 70LCX

B50610 Data Sheet

09/18/09

Broadcom Corporation

Page xx Document B50610-DS07-R

01001).... ..........................................................................................................................................92

Table 62: Auto Power-Down Register (Address 1Ch, Shadow Value 01010) .................................................93

Table 63: External Control 1 Register (Address 1Ch, Shadow Value 01011)..................................................95

Table 64: External Control 2 Register (Address 1Ch, Shadow Value 01100)..................................................96

Table 65: 1000BASE-T/100BASE-TX/10BASE-T LED Selector 1 Register (Address 1Ch, Shadow Value

01101) ..............................................................................................................................................97

Table 66: 1000BASE-T/100BASE-TX/10BASE-T LED Selector 2 Register (Address 1Ch, Shadow Value

01110) ..............................................................................................................................................99

Table 67: 1000BASE-T/100BASE-TX/10BASE-T LED GPIO Control/Status Register

(Address 1Ch, Shadow Value 01111)............................................................................................100

Table 68: 1000BASE-T/100BASE-TX/10BASE-T Master/Slave Seed Register (Address 1Dh) Bit 15=0......101

Table 69: 1000BASE-T/100BASE-TX/10BASE-T HCD Status Register (Address 1Dh) Bit 15=1 .................102

Table 70: 1000BASE-T/100BASE-TX/10BASE-T Test Register 1 (Address 1Eh) ........................................105

Table 71: Expansion Register 00h: Receive/Transmit Packet Counter .........................................................106

Table 72: Expansion Register 04h: Multicolor LED Selector .........................................................................107

Table 73: Expansion Register 05h: Multicolor LED Flash Rate Controls.......................................................109

Table 74: Expansion Register 06h: Multicolor LED Programmable Blink Controls ........................................110

Table 75: Expansion Register 08H: 10BT Controls .......................................................................................111

Table 76: Reset Timing ..................................................................................................................................112

Table 77: REFCLK Input Timing ....................................................................................................................113

Table 78: Management Interface Timing .......................................................................................................114

Table 79: RGMII Input Timing (Normal Mode): GTXCLK and TXD[3:0] ........................................................115

Table 80: RGMII Input Timing (Delayed Mode): GTXCLK and TXD[3:0].......................................................116

Table 81: RGMII Output Timing (Normal Mode): RXC and RXD[3:0] ............................................................117

Table 82: RGMII Output Timing (Delayed Mode): RXC and RXD[3:0] ..........................................................118

Table 83: Absolute Maximum Ratings ........................................................................................................... 119

Table 84: DC Characteristics .........................................................................................................................119

Table 85: Main Differences Between Standard and RoHS-Compliant Packages ..........................................121

Table 86: Theta-JA vs. Airflow for the 100-pin FBGA Package .....................................................................124

Table 87: Theta-JA vs. Airflow for the 48-pin MLP Package..........................................................................124

Table 88: Ordering Information ......................................................................................................................125

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