MT-021
CONVERT START signal. The CONVST signal is a negative-going pulse whose positive-
going edge actually initiates the conversion. The internal sample-and-hold (SHA) amplifier is
placed in the hold mode on this edge, and the various bits are determined using the SAR
algorithm. The negative-going edge of the
CONVST pulse causes the EOC or BUSY line to go
high. When the conversion is complete, the BUSY line goes low, indicating the completion of
the conversion process. In most cases the trailing edge of the BUSY line can be used as an
indication that the output data is valid and can be used to strobe the output data into an external
register. However, because of the many variations in terminology and design, the individual data
sheet should always be consulted when using a specific ADC. An important characteristic of a
SAR ADC is that at the end of the conversion time, the data corresponding to the sampling clock
edge is available with no "pipeline" delay. This makes the SAR ADC especially easy to use in
"single-shot" and multiplexed applications.
It should also be noted that some SAR ADCs require an external high frequency clock in
addition to the CONVERT START command. In most cases there is no need to synchronize the
CONVERT START command to the high frequency clock. The frequency of the external clock,
if required, generally falls in the range of 1 MHz to 30 MHz depending on the conversion time
and resolution of the ADC. Other SAR ADCs have an internal oscillator which is used to
perform the conversions and only require the CONVERT START command. Because of their
architecture, SAR ADCs generally allow single-shot conversion at any repetition rate from dc to
the converter's maximum conversion rate—however, there are some exceptions, so the data sheet
should always be consulted.
Notice that the overall accuracy and linearity of the SAR ADC is determined primarily by the
internal DAC. Until recently, most precision SAR ADCs used laser-trimmed thin-film DACs to
achieve the desired accuracy and linearity. The thin-film resistor trimming process adds cost, and
the thin-film resistor values may be affected when subjected to the mechanical stresses of
packaging.
For these reasons, switched capacitor (or charge-redistribution) DACs have become popular in
newer SAR ADCs. The advantage of the switched capacitor DAC is that the accuracy and
linearity is primarily determined by high-accuracy photolithography, which in turn controls the
capacitor plate area and the capacitance as well as matching. In addition, small capacitors can be
placed in parallel with the main capacitors which can be switched in and out under control of
autocalibration routines to achieve high accuracy and linearity without the need for thin-film
laser trimming. Temperature tracking between the switched capacitors can be better than 1
ppm/ºC, thereby offering a high degree of temperature stability. Modern fine-line CMOS
processes are ideal for the switched capacitor SAR ADC, and the cost is therefore low.
A simple 3-bit capacitor DAC is shown in Figure 3. The switches are shown in the track, or
sample mode where the analog input voltage, A
IN
, is constantly charging and discharging the
parallel combination of all the capacitors. The hold mode is initiated by opening S
IN
, leaving the
sampled analog input voltage on the capacitor array. Switch S
C
is then opened allowing the
voltage at node A to move as the bit switches are manipulated. If S1, S2, S3, and S4 are all
connected to ground, a voltage equal to –A
IN
appears at node A. Connecting S1 to V
REF
adds a
voltage equal to V
REF
/2 to –A
IN
. The comparator then makes the MSB bit decision, and the SAR
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