DEI1016芯片数据手册：ARINC协议支持、自检模式和低功耗功能总览

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DEI1016芯片是一款功能强大的数据传输芯片，具有两个接收器和一个发射器，可广泛应用于各种航空航天领域的通信和数据传输系统中。这款芯片采用了行业标准销钉更换部件，具有全包自检模式，支持25位或32位操作的字长配置，实现了奇偶性接收和传输词的状态和生成。同时，该芯片还配备了8个字发送缓冲器，采用低功耗CMOS技术，支持多种ARINC协议，包括429、571、575、706。此外，DEI1016芯片还提供了扩展温度范围(-55/ 85°C)和军用温度范围(-55/ 125°C)的选择，并可提供QFP、PLCC、LCC和CDIP包装。 DEI1016芯片的出现，为航空航天领域的通信和数据传输系统带来了更高效、更可靠的解决方案，将在未来的发展中发挥重要作用。 ©2020 Device Engineering Inc.Page 1 of 16DS-MW-01016-01 Rev G8/14/2020Features· Two Receivers and One Transmitter· Industry Standard Pin for Pin Replacement Part· Wraparound Self-Test mode· Word length can be configured for 25 bit or 32 bits operation· Parity Status and generation of Receive and Transmit Words· 8 Word Transmitter buffer· Low Power CMOS· Supports multiple ARINC protocols: 429, 571, 575, 706· Available in extended (-55/ 85°C) and Military (-55/ 125°C) temperature ranges· Availabl;".

8/14/2020

Table 6: DEI1016 Control Word

NAME DATA BIT DESCRIPTION

PAREN D4

Transmitter Parity Enable. Enables parity bit insertion into transmitter data bit 32. Parity is

always inserted if /DBCEN is open or HI. If /DBCEN is LO, Logic “0” on PAREN inserts data on

bit 32, and Logic “1” on PAREN inserts parity on bit 32.

/SLFTST

Self Test Enable. Logic “0” enables a “wrap around” test mode which internally connects the

transmitter outputs to both receiver inputs, bypassing the receiver front end. The test data is

inverted before going into receiver 2 so that its data is the complement of that received by

receiver 1. The transmitter output is active during test mode.

SDEN1

S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for

receiver 1.

X1, Y1

D7, D8

S/D compare code RX1. If the receiver 1 S/D code check is enabled (SDENB1=1), then

incoming receiver data S/D fields will be compared to X1, Y1. If they match, the word will be

accepted by receiver 1; if not, it will be ignored. X1 (D7) is compared to serial data bit 9, Y1

(D8) is compared to serial data bit 10.

SDEN2

S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for

receiver 1.

X2, Y2

D10, D11

S/D compare code RX2. If the receiver 2 S/D code check is enabled (SDENB2=1), then

incoming receiver data S/D fields will be compared to X2, Y2. If they match, the word will be

accepted by receiver 2; if not, it will be ignored. X2 (D10) is compared to serial data bit 9, Y2

(D11) is compared to serial data bit 10.

PARCK D12

Parity Check Enable. Logic “1” inverts the transmitter parity bit for test of parity circuits. Logic

“0” selects normal odd parity; logic “1” selects even parity.

TXSEL

D13

Transmitter Data Rate Select. Logic “0” sets the transmitter to the HI data rate. HI rate is equal

to the clock rate divided 10. Logic “1” sets the transmitter to the LO data rate. LO rate is equal

to the clock rate divided by 80.

RCVSEL

D14

Receiver Data Rate Select. Logic “0” sets both receivers to accept the HI data rate. The

nominal HI data rate is the input clock divided by 10. Logic “1” sets both receivers to the LO

data rate. The nominal LO data rate is the input clock divided by 80.

WLSEL

D15

Word Length Select. Logic “0” sets the transmitter and receivers to a 32 bit word format. Logic

”1” sets them to a 25 bit word format.

NOT

USED

D0-D3

When writing to the control register, the four “not used bits” are “don’t care” bits. These four bits

will not be used on the chip.

NOTES

1) The test mode should always conclude with ten null’s. This step prevents both receivers from accepting invalid data.

2) SDENBn, Xn & Yn should be changed within 20 bit times after /DRn goes low and the bit stream has been read, or within 30 bit

times after a master reset has been removed.

3) TXSEL should only be changed during the time that TXR is high or Master Reset is low.

4) RCVSEL should be changed only during a Master Reset pulse. If changed at any other time, then the next bit stream from both

Receiver 1 and Receiver 2 should be ignored.

5) When the control word is written the effect of the WLSEL bit will take effect immediately on the first complete ARINC word recei

ved

or transmitted following the control word write operation.

Functional Description:

The DEI 1016 supports a number of various options

which are selected by data written into the control

the 16-bit data bus when the /LDCW signal is pulsed

to a logic “0”. The twelve control bits control the

following functions:

1) Word Length (32 or 25 bits)

2) Transmitter bit 32 (Parity or Data)

3) Wrap around self test.

4) Source Destination code checking of received

data.

5) Transmitter parity (even or odd)

6) Transmitter and Receiver data rate (100 or 12.5

Table 5: Control Register Format

BIT SYMBOL BIT SYMBOL

D15 (MSB) WLSEL D7 X1

D14 RCVSEL D6 SDENB1

D13 TXSEL D5 /SLFTST

D12 PARCK D4 PAREN

D11 Y2 D3 NOT USED

D10 X2 D2 NOT USED

D9 SDENB2 D1 NOT USED

D8 Y1 D0 NOT USED

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