STM32L151xD-152xD:超低功耗ARM微控制器，详细特性与使用指南

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STM32L151xD-152xD是一系列基于ARM Cortex-M3架构的超低功耗32位微控制器，专为节能应用设计。这款单片机的特点包括广泛的供电范围，从1.65V到3.6V（无内置Brown Out Reset，简称BOR）或1.8V到3.6V，确保了在各种工作条件下都能高效运行。低功耗模式是其核心特性，提供了七种不同的工作模式：Sleep（深度睡眠）、Low-power Run（在32kHz下仅消耗11μA电流）、Low-power Sleep（4.4μA）、Stop模式带有RTC（实时时钟）、Stop模式（仅650nA泄漏电流）、Standby模式带RTC以及更低的Standby模式（300nA）。通过动态时钟频率调整，核心电压可降至233μA/MHz，进一步节省电能。每个I/O引脚的泄漏电流控制在极低的50nA峰值，确保长时间待机时的低能耗。该单片机的核心功能强大，搭载32MHz的ARM Cortex-M3处理器，性能表现优异，Dhrystone 2.1基准测试下每秒可达33.3 DMIPS。集成内存保护单元提供程序和数据的安全性。在电源管理和复位方面，STM32L151xD-152xD支持低功耗、超安全的BOR，同时具备超低功耗的POR（上电复位）和PDR（欠压复位）机制。还内置了可编程电压检测器（PVD），用于系统电压监控。时钟管理方面，单片机配备了一到24MHz的外部晶体振荡器，配合32kHz的RTC振荡器和校准功能。内部有16MHz工厂预调的RC振荡器，以及37kHz低功耗多速RC振荡器，范围从65kHz到4.2MHz。此外，还有一个用于CPU时钟和USB功能的PLL（锁相环路）模块，工作频率高达48MHz。存储方面，STM32L151xD-152xD拥有384KB的闪存，为应用程序和数据提供了足够的存储空间。这些特性使得它在电池驱动设备、无线传感器网络、物联网应用等领域具有广泛的应用潜力，特别是对能源效率有着极高要求的场合。通过合理的功耗管理和灵活的工作模式选择，开发人员可以轻松实现系统级别的能源优化。

Functional overview STM32L151xD, STM32L152xD

16/121 Doc ID 022027 Rev 2

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To

reduce the power consumption in Stop mode, it is possible to automatically switch off the

internal reference voltage (V

REFINT

) in Stop mode. The device remains in reset mode when

is below a specified threshold, V

POR/PDR

or V

BOR

, without the need for any external

reset circuit.

Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-

up time at power-on can be decreased down to 1

ms typically for devices with BOR inactive

at power-up.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. This PVD offers 7 different

levels between 1.85

V and 3.05 V, chosen by software, with a step around 200 mV. An

interrupt can be generated when V

DDA

drops below the V

PVD

threshold and/or when

DDA

is higher than the V

PVD

threshold. The interrupt service routine can then generate

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.3.3 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in Run mode (nominal regulation)

● LPR is used in the Low power run, Low power sleep and Stop modes

● Power down is used in Standby mode. The regulator output is high impedance, the

kernel circuitry is powered down, inducing zero consumption but the contents of the

registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,

LSI, LSE crystal 32K osc, RCC_CSR).

3.3.4 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from Flash memory

● Boot from System memory

● Boot from embedded RAM

The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot

mechanism is available through user option byte, to allow booting from bank 2 when bank 2

contains valid code. This dual boot capability can be used to easily implement a secure field

software update mechanism.

The boot loader is located in System memory. It is used to reprogram the Flash memory by

using USART1, USART2 or USB.

STM32L151xD, STM32L152xD Functional overview

Doc ID 022027 Rev 2 17/121

3.4 Clock management

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low power modes and ensures clock

robustness. It features:

● Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

● Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

● Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

● System clock source: three different clock sources can be used to drive the master

clock SYSCLK:

– 1-24 MHz high-speed external crystal (HSE), that can supply a PLL

– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can

supply a PLL

– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7

frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).

When a 32.768 kHz clock source is available in the system (LSE), the MSI

frequency can be trimmed by software down to a ±0.5% accuracy.

● Auxiliary clock source: two ultralow power clock sources that can be used to drive the

LCD controller and the real-time clock:

– 32.768 kHz low-speed external crystal (LSE)

– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock can be measured using the high-speed internal RC oscillator for

greater precision.

● RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock

the RTC and the LCD, whatever the system clock.

● USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply

the USB interface.

● Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz

clock (MSI). The prescaler ratio and clock source can be changed by the application

program as soon as the code execution starts.

● Clock security system (CSS): this feature can be enabled by software. If a HSE clock

failure occurs, the master clock is automatically switched to HSI and a software

interrupt is generated if enabled.

● Clock-out capability (MCO: microcontroller clock output): it outputs one of the

internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and

APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See

Figure 2 for details on the clock tree.

STM32L151xD, STM32L152xD Functional overview

Doc ID 022027 Rev 2 19/121

3.5 Low power real-time clock and backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain

the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD

(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the

month are made automatically. The RTC provides two programmable alarms and

programmable periodic interrupts with wakeup from Stop and Standby modes.

The programmable wakeup time ranges from 120 µs to 36 hours.

The RTC can be calibrated with an external 512 Hz output, and a digital compensation

circuit helps reduce drift due to crystal deviation.

The RTC can also be automatically corrected with a 50/60Hz stable powerline.

The RTC calendar can be updated on the fly down to sub second precision, which enables

network system synchronisation.

A time stamp can record an external event occurrence, and generates an interrupt.

There are thirty-two 32-bit backup registers provided to store 128 bytes of user application

data. They are cleared in case of tamper detection.

Three pins can be used to detect tamper events. A change on one of these pins can reset

backup register and generate an interrupt. To prevent false tamper event, like ESD event,

these three tamper inputs can be digitally filtered.

3.6 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions, and can be individually

remapped using dedicated AFIO registers. All GPIOs are high-current-capable except for

analog pins. The alternate function configuration of I/Os can be locked if needed following a

specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is

connected to the AHB with a toggling speed of up to 16 MHz.

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge detector lines used to generate

interrupt/event requests. Each line can be individually configured to select the trigger event

(rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected

to the 16 external interrupt lines. The 7 other lines are connected to RTC, PVD, USB or

Comparator events.

Functional overview STM32L151xD, STM32L152xD

20/121 Doc ID 022027 Rev 2

3.7 Memories

The STM32L15xxD devices have the following features:

● 48 Kbyte of embedded RAM accessed (read/write) at CPU clock speed with 0 wait

states. With the enhanced bus matrix, operating the RAM does not lead to any

performance penalty during accesses to the system bus (AHB and APB buses).

● The non-volatile memory is divided into three arrays:

– 384 Kbyte of embedded Flash program memory

– 12 Kbyte of data EEPROM

– Options bytes

Flash program and data EEPROM are divided in two banks, this enables writing in one

bank while running code or reading data in the other bank.

The options bytes are used to write-protect the memory (with 4 KB granularity) and/or

readout-protect the whole memory with the following options:

– Level 0: no readout protection

– Level 1: memory readout protection, the Flash memory cannot be read from or

written to if either debug features are connected or boot in RAM is selected

– Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire)

and boot in RAM selection disabled (JTAG fuse)

The whole non-volatile memory embeds the error correction code (ECC) feature.

3.8 FSMC (flexible static memory controller)

The FSMC supports the following modes: SRAM, PSRAM, NOR Flash.

Functionality overview:

● Up to 26 bit address bus

● Up to 16-bit data bus

● Write FIFO

● Burst mode

● Code execution from external memory

● Four chip select signals

● Up to 32 MHz external access (TBC)

3.9 DMA (direct memory access)

The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management, avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger

support for each channel. Configuration is done by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, SDIO, general-purpose

timers, DAC and ADC.

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