TMS320C6713：高效嵌入式Candence DSP开发指南

tms320c6713

Candence

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TMS320C6713是一款高性能的数字信号处理器(DSP)，专为嵌入式开发人员设计，特别适用于那些需要在Candence软件中进行电路图设计的项目。这款器件以其卓越的性能和丰富的特性吸引了众多工程师的关注。 TMS320C6713的主要特点包括： 1. **极高的运算能力** - 该处理器拥有每周期执行32位指令的能力，支持32/64位数据处理，提供三种时钟频率选项：225 MHz GDP、200 MHz PYP，确保了高效的计算速度。其指令周期时间短，可达4.4至6个周期，这意味着它可以实现高达1800/1350 MIPs (Million Instructions Per Second) 或 1600/1200 MIPs，以及相应的浮点运算性能。 2. **优化的硬件架构** - 它基于先进的Very Long Instruction Word (VLIW) 架构，拥有8个独立的功能单元，包括2个固定点ALUs（算术逻辑单元）、4个同时支持浮点和固定点运算的ALUs，以及2个多功能器，用于浮点和固定点乘法。此外，它采用32位通用寄存器，配合指令打包技术，有助于减小代码大小并提高效率。 3. **丰富的指令集** - TMS320C6713提供了对IEEE 754标准的原生支持，支持单精度和双精度运算，适应不同精度的需求。它的指令集还覆盖了字节地址可寻址性，支持8、16和32位数据操作，确保了广泛的适用性。此外，内置的8位溢出保护机制和饱和、位字段操作、计数等功能，增强了编程灵活性和数据处理准确性。 4. **音频优化** - 针对音频处理应用，TMS320C6713的外围设备集经过精心优化，提供了丰富的接口和加速器，以支持音频信号处理的高效处理。 5. **高效的软件支持** - 配备了高度优化的C/C++编译器，使得开发人员能够编写出更高效、更易维护的代码。 6. **宽温范围** - 除了标准型号外，TMS320C6713还有扩展温度等级的版本，能够在严苛的环境条件下稳定工作。 TMS320C6713 IC 是一个强大的工具，对于那些追求高性能、灵活性和低功耗的嵌入式系统开发者来说，无论是用于信号处理、音频处理还是实时控制等应用场景，都是理想的选择。通过Candence软件，开发者可以轻松地设计和实现复杂的电路图，充分利用这款处理器的潜力。

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SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

memory map summary

Table 3 shows the memory map address ranges of the C6713 device.

Table 3. TMS320C6713 Memory Map Summary

MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE

Internal RAM (L2) 192K 0000 0000 – 0002 FFFF

Internal RAM/Cache 64K 0003 0000 – 0003 FFFF

Reserved 24M – 256K 0004 0000 – 017F FFFF

External Memory Interface (EMIF) Registers 256K 0180 0000 – 0183 FFFF

L2 Registers 128K 0184 0000 – 0185 FFFF

Reserved 128K 0186 0000 – 0187 FFFF

HPI Registers 256K 0188 0000 – 018B FFFF

McBSP 0 Registers 256K 018C 0000 – 018F FFFF

McBSP 1 Registers 256K 0190 0000 – 0193 FFFF

Timer 0 Registers 256K 0194 0000 – 0197 FFFF

Timer 1 Registers 256K 0198 0000 – 019B FFFF

Interrupt Selector Registers 512 019C 0000 – 019C 01FF

Device Configuration Registers 4 019C 0200 – 019C 0203

Reserved 256K − 516 019C 0204 – 019F FFFF

EDMA RAM and EDMA Registers 256K 01A0 0000 – 01A3 FFFF

Reserved 768K 01A4 0000 – 01AF FFFF

GPIO Registers 16K 01B0 0000 – 01B0 3FFF

Reserved 240K 01B0 4000 – 01B3 FFFF

I2C0 Registers 16K 01B4 0000 – 01B4 3FFF

I2C1 Registers 16K 01B4 4000 – 01B4 7FFF

Reserved 16K 01B4 8000 – 01B4 BFFF

McASP0 Registers 16K 01B4 C000 – 01B4 FFFF

McASP1 Registers 16K 01B5 0000 – 01B5 3FFF

Reserved 160K 01B5 4000 – 01B7 BFFF

PLL Registers 8K 01B7 C000 – 01B7 DFFF

Reserved 264K 01B7 E000 – 01BB FFFF

Emulation Registers 256K 01BC 0000 – 01BF FFFF

Reserved 4M 01C0 0000 – 01FF FFFF

QDMA Registers 52 0200 0000 – 0200 0033

Reserved 16M − 52 0200 0034 – 02FF FFFF

Reserved 720M 0300 0000 – 2FFF FFFF

McBSP0 Data Port 64M 3000 0000 – 33FF FFFF

McBSP1 Data Port 64M 3400 0000 – 37FF FFFF

Reserved 64M 3800 0000 – 3BFF FFFF

McASP0 Data Port 1M 3C00 0000 – 3C0F FFFF

McASP1 Data Port 1M 3C10 0000 – 3C1F FFFF

Reserved 1G + 62M 3C20 0000 – 7FFF FFFF

EMIF CE0

†

256M 8000 0000 – 8FFF FFFF

EMIF CE1

†

256M 9000 0000 – 9FFF FFFF

EMIF CE2

†

256M A000 0000 – AFFF FFFF

EMIF CE3

†

256M B000 0000 – BFFF FFFF

Reserved 1G C000 0000 – FFFF FFFF

†

The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space.

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SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

peripheral register descriptions

Table 4 through Table 17 identify the peripheral registers for the C6713 device by its register names, acronyms,

and hex address or hex address range. For more detailed information on the register contents, bit names and

their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals

Overview Reference Guide (literature number SPRU190).

Table 4. EMIF Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

0180 0000 GBLCTL EMIF global control

0180 0004 CECTL1 EMIF CE1 space control

0180 0008 CECTL0 EMIF CE0 space control

0180 000C − Reserved

0180 0010 CECTL2 EMIF CE2 space control

0180 0014 CECTL3 EMIF CE3 space control

0180 0018 SDCTL EMIF SDRAM control

0180 001C SDTIM EMIF SDRAM refresh control

0180 0020 SDEXT EMIF SDRAM extension

0180 0024 − 0183 FFFF − Reserved

Table 5. L2 Cache Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME

0184 0000 CCFG Cache configuration register

0184 4000 L2WBAR L2 writeback base address register

0184 4004 L2WWC L2 writeback word count register

0184 4010 L2WIBAR L2 writeback-invalidate base address register

0184 4014 L2WIWC L2 writeback-invalidate word count register

0184 4020 L1PIBAR L1P invalidate base address register

0184 4024 L1PIWC L1P invalidate word count register

0184 4030 L1DWIBAR L1D writeback-invalidate base address register

0184 4034 L1DWIWC L1D writeback-invalidate word count register

0184 5000 L2WB L2 writeback all register

0184 5004 L2WBINV L2 writeback-invalidate all register

0184 8200 MAR0 Controls CE0 range 8000 0000 − 80FF FFFF

0184 8204 MAR1 Controls CE0 range 8100 0000 − 81FF FFFF

0184 8208 MAR2 Controls CE0 range 8200 0000 − 82FF FFFF

0184 820C MAR3 Controls CE0 range 8300 0000 − 83FF FFFF

0184 8240 MAR4 Controls CE1 range 9000 0000 − 90FF FFFF

0184 8244 MAR5 Controls CE1 range 9100 0000 − 91FF FFFF

0184 8248 MAR6 Controls CE1 range 9200 0000 − 92FF FFFF

0184 824C MAR7 Controls CE1 range 9300 0000 − 93FF FFFF

0184 8280 MAR8 Controls CE2 range A000 0000 − A0FF FFFF

0184 8284 MAR9 Controls CE2 range A100 0000 − A1FF FFFF

0184 8288 MAR10 Controls CE2 range A200 0000 − A2FF FFFF

0184 828C MAR11 Controls CE2 range A300 0000 − A3FF FFFF

0184 82C0 MAR12 Controls CE3 range B000 0000 − B0FF FFFF

0184 82C4 MAR13 Controls CE3 range B100 0000 − B1FF FFFF

0184 82C8 MAR14 Controls CE3 range B200 0000 − B2FF FFFF

0184 82CC MAR15 Controls CE3 range B300 0000 − B3FF FFFF

0184 82D0 − 0185 FFFF − Reserved

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   

SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

peripheral register descriptions (continued)

Table 6. Interrupt Selector Registers

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

019C 0000 MUXH Interrupt multiplexer high

Selects which interrupts drive CPU interrupts

10−15 (INT10−INT15)

019C 0004 MUXL Interrupt multiplexer low

Selects which interrupts drive CPU interrupts 4−9

(INT04−INT09)

019C 0008 EXTPOL External interrupt polarity

Sets the polarity of the external interrupts

(EXT_INT4−EXT_INT7)

019C 000C − 019F FFFF − Reserved

Table 7. Device Registers

HEX ADDRESS RANGE ACRONYM REGISTER DESCRIPTION

019C 0200 DEVCFG Device Configuration

Allows the user to control peripheral selection.

This register also offers the user control of the

EMIF input clock source. For more detailed

information on the device configuration register, see

the Device Configurations section of this data

sheet.

019C 0204 − 019F FFFF − Reserved

N/A CSR CPU Control Status Register

Identifies which CPU and defines the silicon

revision of the CPU. This register also offers the

user control of device operation.

For more detailed information on the CPU Control

Status Register, see the CPU CSR Register

Description section of this data sheet.

Table 8. EDMA Parameter RAM

†

HEX ADDRESS RANGE ACRONYM REGISTER NAME

01A0 0000 − 01A0 0017 − Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event

01A0 0018 − 01A0 002F − Parameters for Event 1 (6 words) or Reload/Link Parameters for other Event

01A0 0030 − 01A0 0047 − Parameters for Event 2 (6 words) or Reload/Link Parameters for other Event

01A0 0048 − 01A0 005F − Parameters for Event 3 (6 words) or Reload/Link Parameters for other Event

01A0 0060 − 01A0 0077 − Parameters for Event 4 (6 words) or Reload/Link Parameters for other Event

01A0 0078 − 01A0 008F − Parameters for Event 5 (6 words) or Reload/Link Parameters for other Event

01A0 0090 − 01A0 00A7 − Parameters for Event 6 (6 words) or Reload/Link Parameters for other Event

01A0 00A8 − 01A0 00BF − Parameters for Event 7 (6 words) or Reload/Link Parameters for other Event

01A0 00C0 − 01A0 00D7 − Parameters for Event 8 (6 words) or Reload/Link Parameters for other Event

01A0 00D8 − 01A0 00EF − Parameters for Event 9 (6 words) or Reload/Link Parameters for other Event

01A0 00F0 − 01A0 00107 − Parameters for Event 10 (6 words) or Reload/Link Parameters for other Event

01A0 0108 − 01A0 011F − Parameters for Event 11 (6 words) or Reload/Link Parameters for other Event

01A0 0120 − 01A0 0137 − Parameters for Event 12 (6 words) or Reload/Link Parameters for other Event

01A0 0138 − 01A0 014F − Parameters for Event 13 (6 words) or Reload/Link Parameters for other Event

01A0 0150 − 01A0 0167 − Parameters for Event 14 (6 words) or Reload/Link Parameters for other Event

01A0 0168 − 01A0 017F − Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event

01A0 0180 − 01A0 0197 − Reload/link parameters for Event 0−15

01A0 0198 − 01A0 01AF − Reload/link parameters for Event 0−15

... ...

01A0 07E0 − 01A0 07F7 − Reload/link parameters for Event 0−15

01A0 07F8 − 01A0 07FF − Scratch pad area (2 words)

†

The C6713 device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.

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