ENC28J60数据手册：独立以太网控制器

需积分: 9 27 浏览量更新于2024-07-23 收藏 1.5MB PDF 举报

"ENC28J60pdf是以太网模块相关的数据手册，主要介绍了一款名为ENC28J60的独立以太网控制器，该控制器具有SPI接口。手册的内容可能涉及设备应用、技术规格以及Microchip公司的免责声明。" 本文档详细介绍了ENC28J60，这是一款独立的以太网控制器，设计用于通过SPI（串行外围接口）与主微控制器通信。这种设计允许嵌入式系统轻松集成以太网功能，而不必依赖于复杂的并行接口。ENC28J60集成了MAC层和PHY层功能，能够处理以太网帧的接收和发送，以及物理层的数据传输。该数据手册可能会涵盖以下关键知识点： 1. SPI接口：SPI是一种常见的串行通信协议，通常用于低速、短距离通信。ENC28J60的SPI接口使得它能与各种微控制器兼容，只需要较少的信号线即可实现数据交换。 2. 以太网功能：ENC28J60支持10Base-T以太网标准，可以处理10Mbps的数据速率。它包含了MAC地址存储、帧过滤、校验和计算等功能，使得嵌入式系统能接入局域网。 3. 硬件特性：可能包括PHY状态寄存器、MAC控制寄存器、以及接收和发送缓冲区的管理。这些特性有助于用户理解和配置控制器以满足不同应用的需求。 4. 驱动程序和支持：数据手册可能提供了驱动程序的开发指南，以及如何与微控制器上的软件进行交互的方法，帮助开发者快速集成ENC28J60到他们的系统中。 5. 电源和功耗：ENC28J60的电源需求和工作电流，对于电源设计和电池供电的应用尤其重要。 6. 抗干扰和电磁兼容性(EMC)：控制器的电磁兼容性设计，保证了在复杂电磁环境中稳定工作。 7. 错误检测和纠正机制：如CRC校验等，用于确保数据传输的可靠性。 8. Microchip的免责声明：Microchip Technology Inc.明确表示，提供的信息仅供参考，可能会有更新，并且不提供任何形式的保证。用户有责任确保其应用符合技术规范，并且在使用Microchip器件（如ENC28J60）于生命支持和/或安全应用时，风险自负。Microchip不承担由此产生的任何损害、索赔或费用。在实际应用中，开发人员应仔细阅读此数据手册，了解ENC28J60的所有特性和操作限制，以确保其设计满足项目需求并遵循所有相关的技术标准。此外，对于使用ENC28J60的生命周期支持和安全应用，开发者需要自行承担风险并确保满足所有的法规要求，同时保护Microchip免受任何潜在的责任。

ENC28J60

EPMCSL Pattern Match Checksum Low Byte (EPMCS<7:0>) 0000 0000 51

EPMCSH Pattern Match Checksum High Byte (EPMCS<15:0>) 0000 0000 51

EPMOL Pattern Match Offset Low Byte (EPMO<7:0>) 0000 0000 51

EPMOH

— — — Pattern Match Offset High Byte (EPMO<12:8>) ---0 0000 51

ERXFCON UCEN ANDOR CRCEN PMEN MPEN HTEN MCEN BCEN 1010 0001 48

EPKTCNT Ethernet Packet Count 0000 0000 43

MACON1

— — — r TXPAUS RXPAUS PASSALL MARXEN ---0 0000 34

MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX 0000 0000 35

MACON4

— DEFER BPEN NOBKOFF — —r r-000 --00 36

MABBIPG

— Back-to-Back Inter-Packet Gap (BBIPG<6:0>) -000 0000 36

MAIPGL

— Non-Back-to-Back Inter-Packet Gap Low Byte (MAIPGL<6:0>) -000 0000 34

MAIPGH

— Non-Back-to-Back Inter-Packet Gap High Byte (MAIPGH<6:0>) -000 0000 34

MACLCON1

— — — — Retransmission Maximum (RETMAX<3:0>) ---- 1111 34

MACLCON2

— — Collision Window (COLWIN<5:0>) --11 0111 34

MAMXFLL Maximum Frame Length Low Byte (MAMXFL<7:0>) 0000 0000 34

MAMXFLH Maximum Frame Length High Byte (MAMXFL<15:8>) 0000 0110 34

MICMD

— — — — — — MIISCAN MIIRD ---- --00 21

MIREGADR

— — — MII Register Address (MIREGADR<4:0>) ---0 0000 19

MIWRL MII Write Data Low Byte (MIWR<7:0>) 0000 0000 19

MIWRH MII Write Data High Byte (MIWR<15:8>) 0000 0000 19

MIRDL MII Read Data Low Byte (MIRD<7:0>) 0000 0000 19

MIRDH MII Read Data High Byte(MIRD<15:8>) 0000 0000 19

MAADR5 MAC Address Byte 5 (MAADR<15:8>) 0000 0000 34

MAADR6 MAC Address Byte 6 (MAADR<7:0>) 0000 0000 34

MAADR3 MAC Address Byte 3 (MAADR<31:24>), OUI Byte 3 0000 0000 34

MAADR4 MAC Address Byte 4 (MAADR<23:16>) 0000 0000 34

MAADR1 MAC Address Byte 1 (MAADR<47:40>), OUI Byte 1 0000 0000 34

MAADR2 MAC Address Byte 2 (MAADR<39:32>), OUI Byte 2 0000 0000 34

EBSTSD Built-in Self-Test Fill Seed (EBSTSD<7:0>) 0000 0000 76

EBSTCON PSV2 PSV1 PSV0 PSEL TMSEL1 TMSEL0 TME BISTST 0000 0000 75

EBSTCSL Built-in Self-Test Checksum Low Byte (EBSTCS<7:0>) 0000 0000 76

EBSTCSH Built-in Self-Test Checksum High Byte (EBSTCS<15:8>) 0000 0000 76

MISTAT

— — — — r NVALID SCAN BUSY ---- 0000 21

EREVID

(2)

— — — Ethernet Revision ID (EREVID<4:0>) ---q qqqq 22

ECOCON

(3)

— — — — — COCON2 COCON1 COCON0 ---- -100 6

EFLOCON

— — — — — FULDPXS FCEN1 FCEN0 ---- -000 56

EPAUSL Pause Timer Value Low Byte (EPAUS<7:0>) 0000 0000 57

EPAUSH Pause Timer Value High Byte (EPAUS<15:8>) 0001 0000 57

TABLE 3-2: ENC28J60 CONTROL REGISTER SUMMARY (CONTINUED)

Value

Reset

Details

Page

Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition, r = reserved, do not modify.

Note 1: CLKRDY resets to ‘0’ on Power-on Reset but is unaffected on all other Resets.

2: EREVID is a read-only register.

3: ECOCON resets to ‘---- -100’ on Power-on Reset and ‘---- -uuu’ on all other Resets.

ENC28J60

3.2 Ethernet Buffer

The Ethernet buffer contains transmit and receive

memory used by the Ethernet controller. The entire

buffer is 8 Kbytes, divided into separate receive and

transmit buffer spaces. The sizes and locations of

transmit and receive memory are fully programmable

by the host controller using the SPI interface.

The relationship of the buffer spaces is shown in

Figure 3-2.

3.2.1 RECEIVE BUFFER

The receive buffer constitutes a circular FIFO buffer

managed by hardware. The register pairs

ERXSTH:ERXSTL and ERXNDH:ERXNDL serve as

Pointers to define the buffer’s size and location within

the memory. The byte pointed to by ERXST and the

byte pointed to by ERXND are both included in the

FIFO buffer.

As bytes of data are received from the Ethernet

interface, they are written into the receive buffer

sequentially. However, after the memory pointed to by

ERXND is written to, the hardware will automatically

write the next byte of received data to the memory

pointed to by ERXST. As a result, the receive hardware

will never write outside the boundaries of the FIFO.

The host controller may program the ERXST and

ERXND Pointers when the receive logic is not enabled.

The Pointers must not be modified while the receive

logic is enabled (ECON1.RXEN is set). If desired, the

Pointers may span the 1FFFh to 0000h memory

boundary; the hardware will still operate as a FIFO.

The ERXWRPTH:ERXWRPTL registers define a

location within the FIFO where the hardware will write

bytes that it receives. The Pointer is read-only and is

automatically updated by the hardware whenever a

new packet is successfully received. The Pointer is

useful for determining how much free space is

available within the FIFO.

The ERXRDPT registers define a location within the

FIFO where the receive hardware is forbidden to write

to. In normal operation, the receive hardware will write

data up to, but not including, the memory pointed to by

ERXRDPT. If the FIFO fills up with data and new data

continues to arrive, the hardware will not overwrite the

previously received data. Instead, the new data will be

thrown away and the old data will be preserved. In

order to continuously receive new data, the host con-

troller must periodically advance this Pointer whenever

it finishes processing some, or all, of the old received

data.

3.2.2 TRANSMIT BUFFER

Any space within the 8-Kbyte memory, which is not

programmed as part of the receive FIFO buffer, is

considered to be the transmit buffer. The responsibility

of managing where packets are located in the transmit

buffer belongs to the host controller. Whenever the host

controller decides to transmit a packet, the ETXST and

ETXND Pointers are programmed with addresses

specifying where, within the transmit buffer, the partic-

ular packet to transmit is located. The hardware does

not check that the start and end addresses do not

overlap with the receive buffer. To prevent buffer

corruption, the host controller must make sure to not

transmit a packet while the ETXST and ETXND

Pointers are overlapping the receive buffer, or while the

ETXND Pointer is too close to the receive buffer. See

Section 7.1 “Transmitting Packets” for more

information.

3.2.3 READING AND WRITING TO

THE BUFFER

The Ethernet buffer contents are accessed from the

host controller though separate Read and Write Point-

ers (ERDPT and EWRPT) combined with the read

buffer memory and write buffer memory SPI

commands. While sequentially reading from the

receive buffer, a wrapping condition will occur at the

end of the receive buffer. While sequentially writing to

the buffer, no wrapping conditions will occur. See

Section 4.2.2 “Read Buffer Memory Command” and

Section 4.2.4 “Write Buffer Memory Command” for

more information.

3.2.4 DMA ACCESS TO THE BUFFER

The integrated DMA controller must read from the buffer

when calculating a checksum and it must read and write

to the buffer when copying memory. The DMA follows

the same wrapping rules that SPI accesses do. While it

sequentially reads, it will be subject to a wrapping condi-

tion at the end of the receive buffer. All writes it does will

not be subject to any wrapping conditions. See

Section 13.0 “Direct Memory Access Controller” for

more information.

剩余95页未读，继续阅读

qiaojia202020

粉丝: 0
资源: 1

ENC28J60数据手册：独立以太网控制器

ENC28J60_AT89S52.rar_ C51 ENC28J60_AT89S52_ENC28J60_enc28j60 C

NET-ENC28J60.rar_ENC28J60_ENC28J60 HR911105A_ENC28J60 hr911105a

ENC28J60.pdf

ENC28J60_ENC28J60_zip_

ENC28J60-H.pdf

uIP协议栈+ENC28J60 网卡.pdf

以太网ENC28J60[归纳].pdf

ENC28J60资料

ENC28J60最小封装以太网络芯片.pdf

基于ENC28J60以太网控制器及其应用.pdf

最新资源