TI LMK5B12204：超低抖动网络同步器时钟解决方案
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TI-LMK5B12204是一款高性能网络同步器时钟芯片，专为满足通信基础设施和工业应用的严格时序需求而设计。该器件集成了先进的数字和模拟锁相环(DPLL和APLL)技术，提供超低抖动和电源噪声抑制能力，从而显著降低高速串行链路的误码率(BER)。
1. **特性**
- **数字锁相环(DPLL)**：支持无中断切换，相位瞬态精度高达±50ps，具有快速锁定功能的可编程环路带宽。此外，它能配合低成本的晶体振荡器(TCXO/OCXO)实现标准同步和保持模式。
- **模拟锁相环(APLL)**：包含两个APLL，分别在312.5MHz和155.52MHz频率下提供业界领先的50fsRMS和125fsRMS的低抖动输出。
- **基准时钟输入**：支持两个输入，基于优先级选择，并能在参考时钟缺失时进入数字保持模式。
- **时钟输出**：提供四个可编程驱动器的时钟输出，支持四种不同的输出格式：AC-LVDS、AC-CML、AC-LVPECL和1.8V LVCMOS。
- **自定义时钟配置**：支持1Hz至800MHz的输入频率，10MHz至100MHz的XO/TCXO/OCXO输入，以及DCO模式下的精细时钟控制。
- **接口**：提供I2C或SPI接口，用于灵活配置和先进的时钟监控。
- **电源与温度**：3.3V电源，可提供1.8V、2.5V或3.3V输出，工作温度范围为-40°C至+85°C。
- **性能指标**：电源噪声抑制比(PSNR)达到-83dBc，确保高信号质量。
2. **应用**
- **网络同步**：适用于SyncE(G.8262)、SONET/SDH、IEEE1588 PTP从时钟和光传输网络(G.709)。
- **高速网络设备**：如400G线卡和网络卡，用于以太网交换机和路由器。
- **无线通信**：无线基站(BTS)和无线回程系统。
- **测试与测量**：在精密测量设备中发挥作用。
- **医疗成像**：支持对时序要求严格的医疗设备。
- **数据处理**：为56G/112GPAM-4PHY、ASIC、FPGA、SoC和处理器提供抖动消除、漂移衰减和基准时钟生成服务。
3. **功能说明**
LMK5B12204利用其内置的BAW VCO技术，能够生成低至50fsRMS抖动的输出时钟，且不受外部XO和基准输入的影响。这种超低抖动性能对于需要高数据速率和可靠性的应用至关重要。此外，器件提供了全面的时钟监控和状态报告功能，增强了系统的可靠性。
TI-LMK5B12204是一款功能强大的时钟解决方案，其出色的性能和灵活性使其成为各种通信和工业应用的理想选择，特别是在需要低抖动和高稳定性的时钟源时。
Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY NOISE REJECTION (PSNR) / CROSSTALK SPURS
PSNR
50mV
Spur induced by power supply
noise (V
N
= 50 mVpp)
(6)
(7)
V
DD
= 3.3 V, V
DDO_x
= 3.3 V, 156.25
MHz, AC-DIFF output
–83
dBc
V
DD
= 3.3 V, V
DDO_x
= 3.3 V, 156.25
MHz, HCSL output
–78
dBc
PSNR
25mV
Spur induced by power supply
noise (V
N
= 25 mVpp)
(6)
(7)
V
DD
= 3.3 V, V
DDO_x
= 1.8 V, 156.25
MHz, AC-DIFF output
–63
dBc
V
DD
= 3.3 V, V
DDO_x
= 1.8 V, 156.25
MHz, HCSL output
–58
dBc
V
DD
= 3.3 V, V
DDO_x
= 1.8 V, 156.25
MHz, LVCMOS output
–45
dBc
SPUR
XTALK
Spur level due to output-to-output
crosstalk (adjacent channels)
(7)
f
OUTx
= 156.25 MHz, f
OUTy
= 155.52
MHz, AC-LVPECL
–75
dBc
SPUR
Highest spur level within 12 kHz
to 40 MHz band (excludes output
crosstalk and integer-boundary
spurs)
(7)
f
VCO1
= 2500 MHz, f
VCO2
= 6065.28
MHz, f
OUTx
= 156.25 MHz, f
OUTy
=
155.52 MHz, AC-LVPECL
–80
dBc
PLL CLOCK OUTPUT PERFORMANCE CHARACTERISTICS
RJ
RMS Phase Jitter (12 kHz to 20
MHz)
(14)
312.5 MHz AC-LVPECL output from
APLL1, f
XO
= 48.0048 MHz, f
PD1
=
f
XO
/2, f
VCO1
= 2.5 GHz
50 80 fs RMS
RMS Phase Jitter (12 kHz to 20
MHz)
(14)
156.25 MHz AC-LVPECL output from
APLL1, f
XO
= 48.0048 MHz, f
PD1
=
f
XO
/2, f
VCO1
= 2.5 GHz
60 90 fs RMS
RMS Phase Jitter (12 kHz to 20
MHz)
(14)
153.6 MHz AC-LVPECL output from
APLL2, f
XO
= 48.0048 MHz, f
PD1
=
f
XO
/2, f
VCO1
= 2.5 GHz, f
PD2
= f
VCO1
/18,
f
VCO2
= 5.5296 GHz
125 200 fs RMS
RMS Phase Jitter (12 kHz to 20
MHz)
(14)
155.52 MHz AC-LVPECL output from
APLL2, f
XO
= 48.0048 MHz, f
PD1
=
f
XO
/2, f
VCO1
= 2.5 GHz, f
PD2
= f
VCO1
/18,
f
VCO2
= 5.59872 GHz
125 200 fs RMS
BW DPLL bandwidth range
(8)
Programmed bandwidth setting 0.01 4000 Hz
J
PK
DPLL closed-loop jitter
peaking
(10)
f
REF
= 25 MHz, f
OUT
= 10 MHz, DPLL
BW = 0.1 Hz or 10 Hz
0.1 dB
J
TOL
Jitter tolerance
Jitter modulation = 10 Hz, 25.78125
Gbps
6455 UI p-p
t
HITLESS
Phase hit between two reference
inputs with 0 ppm error
Valid for a single switchover event
between two clock inputs at the same
frequency
± 50 ps
f
HITLESS
Frequency transient during hitless
switch
Valid for a single switchover event
between two clock inputs at the same
frequency
± 10 ppb
(1) Total device current can be estimated by summing the individual IDD_x and IDDO_x per pin for all blocks enabled in a
given configuration.
(2) Configuration A (All PLL blocks on except APLL2 is disabled): f
REF
= 25 MHz, f
XO
= 48.0048 MHz, f
VCO1
= 2.5 GHz.
(3) IDDO_x current for an operating output is the sum of mux, divider, and an output format.
(4) For a differential input clock below 5 MHz, TI recommends to disable the differential input amplitude monitor and enable at least one
other monitor (frequency, window detectors) to validate the input clock. Otherwise, consider using an LVCMOS clock for an input
below 5 MHz.
(5) An output frequency over f
OUT
max spec is possible, but output swing may be less than V
OD
min specification.
(6) PSNR is the single-sideband spur level (in dBc) measured when sinusoidal noise with amplitude V
N
and frequency f
N
(between 100
kHz and 1 MHz) is injected onto VDD and VDDO_x pins.
(7) DJ
SPUR
(ps pk-pk) = [2 × 10
(dBc/20)
/ (π × f
OUT
) × 1E6], where dBc is the PSNR or SPUR level (in dBc) and f
OUT
is the output frequency
(in MHz).
(8) Actual loop bandwidth may be lower. The valid loop bandwidth range may be constrained by the DPLL TDC frequency used in a given
configuration.
www.ti.com.cn
LMK5B12204
ZHCSLM0A – MAY 2020 – REVISED JANUARY 2021
Copyright © 2021 Texas Instruments Incorporated
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