Vivado IP定制教程：创建、验证与打包指南

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本资源是Xilinx Vivado Design Suite的用户指南，专注于创建、定制和打包自定义IP（知识产权）功能。版本为2017.3，发布日期为2017年10月4日，涵盖了Vivado工具的最新特性与更新。 1. **创建和包装定制IP**：在这份手册中，用户可以学习如何在Vivado环境中从头开始创建新的IP模块，包括设计顶层硬件描述语言（HDL）规范，如AXI4接口的添加和自定义外围设备的设计。第一章介绍了基本步骤，包括对顶层HDL要求的重要注意事项，强调了代码的可修改性和元数据管理的重要性。 2. **验证IP和参考**：第三章着重于IP的验证，提供了验证IP的实用建议，并新增了针对Introduction的部分，推荐使用Verification IP进行功能和性能测试。同时，对于使用Create and Package IP Wizard的指南，添加了重要的提示，确保正确使用IP开发流程。 3. **XPM（Xilinx Parameterized IP）使用**：该部分给出了关于在设计过程中如何有效地使用Xilinx Parameterized IP（XPM）的建议，帮助用户在保持设计灵活性的同时，实现快速配置和复用。 4. **处理HLS（High-Level Synthesis）文件**：当涉及到打包特定目录时，针对HLS源代码中的文件管理，手册提供了一份关于处理相关文件的重要注意事项，以确保HLS生成的IP能够顺利整合到设计中。 5. **升级自定义IP**：第二章详细讨论了如何升级现有的定制IP，包括对子核心IP的扩展定义和处理代码加密的升级策略。 6. **Synthesis and Implementation加密**：对于代码安全性的关注，第六章的文本被修改，明确了Xilinx_enable_modification/xilinx-specific部分，指出在Synthesis和Implementation阶段，不允许对生成的Netlist进行修改，强调了IP设计的固有特性。 7. **视频辅助与加密示例**：新增的快速视频教程和加密代码示例，为用户提供了一种直观且安全的方式来理解和实践IP打包过程。这份Vivado IP Custom Manual为设计者提供了全面的指导，从创建基础IP到高级定制和打包技巧，旨在提升用户在Xilinx Vivado平台上的工作效率和IP质量。无论是初次接触还是经验丰富的开发人员，都能从中找到有价值的信息。

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Chapter 2: IP Packaging Basics

Packaging a Design with Global Include Files

The Vivado IDE supports designating Verilog or Verilog Header files as global `include

files to process before any other sources.

Note:

This feature is not supported when packaging a custom IP.

After packaging, the Vivado tool treats global `include files as standard Verilog or Verilog

Header files.

To package a design that uses global ‘include files, you must modify the HDL to place the

`include statement at the top of any Verilog source file that references content from

another Verilog or Verilog header file.

Constraints Requirements

The IP packager supports constraints files (XDC) along with RTL files. The following are the

supported XDC file types:

• XDC to be used during synthesis and implementation (default)

• XDC to be used only during implementation

• XDC for use only during out-of-context (OOC) synthesis

This section describes the following concepts:

• Managing Out-of-Context Constraints

• Processing Order of Constraints

For more details on IP constraints, see Vivado Design Suite User Guide: Using Constraints

(UG903) [Ref 12], and for constraints in general see Vivado Design Suite User Guide:

Synthesis (UG901) [Ref 11].

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Chapter 2: IP Packaging Basics

Managing Out-of-Context Constraints

By default, IP are synthesized out-of-context (OOC) of the top-level design. When you use

the out-of-context flow, an OOC flow-only XDC is required for sequential logic timing

during Vivado synthesis. This XDC file provides clock definitions for clocks from the

top-level, either from the user or from another IP.

When creating your custom IP, it is recommended that you include an OOC XDC file to

provide these clock definitions for synthesizing the IP standalone.

For more information on the OOC flow, see the following documents:

Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9]

Vivado Design Suite User Guide: Synthesis (UG901) [Ref 11]

Note:

For Xilinx delivered IP, the OOC XDC file has _ooc appended to the filename. This is not a

requirement, because the USED_IN file property determines if it is an OOC XDC file, not the

filename.

In a typical design, an IP receives some of its required constraints from the top-level design.

For example, if your custom IP does not directly interface with the device boundary, it

typically relies on the parent design to supply the input clock definitions. The OOC XDC file

generally only contains these input clock definitions. This is required so that clock

definitions exist when the IP is synthesized OOC of the top-level constraints. While this is

not a requirement, it is not recommended to add any additional constraint types. During

implementation of the entire design, the IP netlists link with the top-level netlist and the

OOC XDC is not required.

There are two instances in which an IP must have the input clock definition in the IP XDC file

instead of the OOC XDC file, which are, as follows:

IP contains a clock definition connected to an input buffer

IP contains a clock definition internal to the IP

In OOC mode, Vivado synthesis does not insert I/O buffers.

If your custom IP port has an instantiated input buffer, leave the input clock

definition in your IP XDC file.

If the input clock definition is defined on an internal element of the IP, such as a

Flip-Flop or a GT, leave the input clock definition in the IP XDC file.

If your use case does not fall into one of the two categories, move the clock

definition to the OOC XDC file.

After the OOC XDC file is created, set the USED_IN property to out_of_context. This

marks the XDC file to be processed in the OOC flow only.

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Chapter 2: IP Packaging Basics

IMPORTANT: The USED_IN property for an OOC XDC file should be {synthesis implementation

out_of_context}. If it is only set to out_of_context, it is not used during synthesis or

implementation.

Processing Order of Constraints

The Vivado IP that deliver constraints are processed either before or after the user design

constraints. For more information on using constraints, see this link in the Vivado Design

Suite User Guide: Using Constraints (UG903) [Ref 12].

IMPORTANT: An XDC marked as OUT_OF_CONTEXT is processed before all other XDC files used in the

IP, including those marked to have a PROCESSING_ORDER value of EARLY. The default value of

PROCESSING_ORDER is NORMAL. There is also a LATE value.

When creating your custom IP, you must determine the order in which the constraints are

processed in the context of a user design. The IP packager inherits the processing order set

on the constraint files in the project. Set these properties properly in your project prior to

packaging the IP. The constraints delivered for an IP only support two processing orders:

EARLY and LATE. All constraints marked as the default of NORMAL are converted to EARLY.

By default, top-level user constraints have the processing order set to NORMAL, which

comes between EARLY and LATE. This way an IP can provide output clocks that the

top-level reference in an EARLY XDC as well as allow for the top-level constraints to

override an IP constraint if needed.

If an IP constraint has a dependency to a top-level constraint, such as a top-level clock

object, place the constraint in an XDC marked as LATE. This ensures that the required

object is present when the IP constraint is processed. In the case of the IP being synthesized

out-of-context, the OOC XDC provides the top-level clock object.

Note:

Xilinx IP XDC files that have their PROCESSING_ORDER property set to LATE are named

<IP_NAME>_clocks.xdc. This naming convention is not required for a custom IP.

Most constraints for an IP belong in the EARLY processing order. The constraints marked

for LATE require user constraints prior to processing. This generally refers to clock

dependencies.

Upgrading Custom IP

A custom IP upgrades as every other IP in the Vivado IP catalog. The difference is how the

custom IP is edited to create a new version or revision to which to upgrade. For more

information on the process of upgrading IP, see this link in the Vivado Design Suite User

Guide: Designing with IP (UG896) [Ref 9].

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Chapter 2: IP Packaging Basics

For custom IP, you do not have to upgrade when a newer version is available in the IP

catalog. All versions, if accessible in the IP catalog, are available for customization and use;

however, when using Xilinx IP in your custom IP, moving to a new Vivado release could

cause the custom IP to become locked.

This IP lock is because the IP used in the custom IP must be upgraded. If you do not want

to update any information for the custom IP, you must ensure all the output products are

fully generated from the previously supported release.

IMPORTANT: For Xilinx IP, only one version of an IP is delivered in each release of the Vivado Design

Suite.

In the report IP status example, shown in the following figure, the status reports the IP

definition has missing subcores.

In this case, the sub-core IP, any IP that is associated to the design that is not Hierarchical or

Subsystem IP (IP from the Vivado IP catalog, user-defined IP, third-party IP, or IP core

libraries), is missing because the Xilinx IP used by the custom IP has a new version. Because

Vivado only supports the latest version of a Xilinx IP, the previous version originally used

when creating the custom IP no longer exists.

To create a new version of the custom IP:

1. Edit the IP in an Editing IP project or in the original project from which the IP was

packaged. For more information on creating and using an Editing IP project, see the

Editing an Existing Custom IP section.

RECOMMENDED: Review the Versioning and Revision Control section to understand how to properly

maintain versions of your custom IP.

2. In the Vivado project used to edit the custom IP, upgrade the Xilinx IP. After the upgrade

of the IP is complete, ensure that the custom IP operates as expected and make any

additional modifications to keep functionality.

3. After the custom IP is updated with the necessary changes, ensure the Package IP

window has fully merged the changes and repackage the IP. For more information on the

Package IP window, see Packaging a Specified Directory in Chapter 3.

X-Ref Target - Figure 2-1

Figure 2-1: Locked Custom IP in Report IP Status View

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