MIPS32 4KEc 处理器核心数据手册

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"MIPS32™4KEc™Processor Core Datasheet" 本文档详细介绍了MIPS32™4KEc™处理器核心，这是一款由MIPS Technologies Inc.开发的高性能、低功耗32位MIPS RISC（精简指令集计算机）核心。该核心特别适用于定制的系统级硅片应用。它面向半导体制造商、ASIC开发者以及希望快速将自定义逻辑和外围设备与高性能RISC处理器集成的系统原始设备制造商。 4KEc核心的设计高度可移植，能在不同工艺流程中无缝适应，便于集成到完整的系统级硅片设计中，使开发者可以专注于终端用户产品的开发。这一特性使得4KEc核心在数字消费、网络、系统和信息管理市场的新兴领域中处于理想位置，能够支持针对嵌入式应用的定制化解决方案。 4KEc核心实现了MIPS32 Release 2架构，并且包含了MIPS16e™ ASE（应用特定扩展）。MIPS32 Release 2架构是MIPS指令集的一个版本，提供了一套强大的指令集，适合实现高效的32位计算。MIPS16e ASE则是一个节能的16位指令集，旨在为需要节省代码空间的应用提供更高的效率，同时保持与32位操作的兼容性。此外，4KEc核心还集成了32位特权资源架构，这意味着它不仅提供了用户级别的执行环境，还支持操作系统和其他需要访问特权硬件资源的软件。这包括内存管理单元（MMU）、中断处理机制以及虚拟内存等关键功能，这些对于构建复杂的嵌入式系统是至关重要的。 4KEc核心的特性还包括其低功耗设计，这对于电池供电或对能源效率有严格要求的设备至关重要。它的高效性能使得它可以运行在各种各样的应用中，从嵌入式控制系统到高性能的消费电子产品。文档中可能还会详细描述核心的时钟速度、功耗数据、寄存器结构、总线接口规范、调试选项以及其他设计特点，如指令预取、超标量执行、乱序执行和分支预测等，这些都为优化性能和系统响应时间提供了可能。 MIPS32™4KEc™处理器核心是一款强大而灵活的微处理器设计，为嵌入式系统设计者提供了丰富的工具和资源，以满足他们在性能、功耗和定制化方面的需求。通过深入理解这个核心的特性，开发者可以更有效地利用其优势，打造出满足市场需求的创新产品。

8 MIPS32™ 4KEc™ Processor Core Datasheet, Revision 02.00

modes with the same capability. This is done by

introducing multiple copies of the GPRs, called shadow

sets, and allowing privileged software to associate a

shadow set with entry to kernel mode via an interrupt

vector or exception. The normal GPRs are logically

considered shadow set zero.

The number of GPR shadow sets is a build-time option on

the 4KEc core. Although Release 2 of the Architecture

deﬁnes a maximum of 16 shadow sets, the core allows one

(the normal GPRs), two, or four shadow sets. The highest

number actually implemented is indicated by the

SRSCtl

HSS

ﬁeld. If this ﬁeld is zero, only the normal GPRs

are implemented.

Shadow sets are new copies of the GPRs that can be

substituted for the normal GPRs on entry to kernel mode

via an interrupt or exception. Once a shadow set is bound

to a kernel mode entry condition, reference to GPRs work

exactly as one would expect, but they are redirected to

registers that are dedicated to that condition. Privileged

software may need to reference all GPRs in the register ﬁle,

even speciﬁc shadow registers that are not visible in the

current mode. The RDPGPR and WRPGPR instructions

are used for this purpose. The CSS ﬁeld of the SRSCtl

set, and the PSS ﬁeld of the SRSCtl register provides the

number of the previous shadow register set (that which was

current before the last exception or interrupt occurred).

If the processor is operating in VI interrupt mode, binding

of a vectored interrupt to a shadow set is done by writing to

the SRSMap register. If the processor is operating in EIC

interrupt mode, the binding of the interrupt to a speciﬁc

shadow set is provided by the external interrupt controller,

and is conﬁgured in an implementation-dependent way.

Binding of an exception or non-vectored interrupt to a

shadowset is done by writing to the ESS ﬁeld of the SRSCtl

of SRSCtl

CSS

is copied to SRSCtl

PSS

, and SRSCtl

CSS

is set

to the value taken from the appropriate source. On an

ERET, the value of SRSCtl

PSS

is copied back into

SRSCtl

CSS

to restore the shadow set of the mode to which

control returns.

Modes of Operation

The 4KEc core supports three modes of operation: user

mode, kernel mode, and debug mode. User mode is most

often used for applications programs. Kernel mode is

typically used for handling exceptions and operating

system kernel functions, including CP0 management and I/

O device accesses. An additional Debug mode is used

during system bring-upandsoftwaredevelopment. Refer to

the EJTAG section for more information on debug mode.

Figure 3 4KEc Core Virtual Address Map

Memory Management Unit (MMU)

The 4KEc core contains a fully functional MMU that

interfaces between the execution unit and the cache

controller. Although the 4KEc core implements a 32-bit

architecture, the MMU is modeled after that found in the

64-bit R4000 family, as deﬁned by the MIPS32 Privileged

Resource Architecture (PRA).

The 4KEc core implements a TLB-based MMU. The TLB

consists of three translation buffers: a 16 dual-entry fully

associative Joint TLB (JTLB), a 4-entry fully associative

Instruction TLB (ITLB) and a 4-entry fully associative data

TLB (DTLB).

When an instruction address is calculated, the virtual

address is compared to the contents of the 4-entry ITLB. If

kuseg

kseg0

kseg1

kseg2

kseg3

0x00000000

0x7FFFFFFF

0x80000000

0x9FFFFFFF

0xA0000000

0xBFFFFFFF

0xC0000000

0xDFFFFFFF

0xE0000000

0xF1FFFFFF

Kernel virtual address space

Unmapped, 512 MB

Kernel virtual address space

Uncached

Unmapped, 512 MB

Kernel virtual address space

User virtual address space

1. This space is mapped to memory in user or kernel mode,

and by the EJTAG module in debug mode.

0xFF200000

0xFF3FFFFF

0xFF400000

0xFFFFFFFF

Memory/EJTAG

Mapped, 2048 MB

Mapped, 512 MB

Memory Mapped

MIPS32™ 4KEc™ Processor Core Datasheet, Revision 02.00 9

the address is not found in the ITLB, the JTLB is accessed.

If the entry is found in the JTLB, that entry is then written

into the ITLB. If the address is not found in the JTLB, a

TLB reﬁll exception is taken.

When a data address is calculated, the virtual address is

compared to both the 4-entry DTLB and the JTLB. If the

address is not found in the DTLB, but is found in the JTLB,

that address is immediately written to the DTLB. If the

address is not found in the JTLB, a TLB reﬁll exception is

taken.

Figure 4 shows how the ITLB, DTLB, and JTLB are

implemented in the 4KEc core.

Figure 4 Address Translation During a Cache Access

Translation Lookaside Buffer (TLB)

The TLB consists of three address translation buffers:

• 16 dual-entry fully associative Joint TLB (JTLB)

• 4-entry fully associative Instruction TLB (ITLB)

• 4-entry fully associative Data TLB (DTLB)

Joint TLB (JTLB)

The 4KEc core implements a 16-dual-entry, fully

associative JTLB that maps 32 virtual pages to their

corresponding physical addresses. The purpose of the TLB

is to translate virtual addresses and their corresponding

ASIDs into a physical memory address. The translation is

performed by comparing the upper bits of the virtual

address (along with the ASID) against each of the entries in

the tag portion of the joint TLB structure.

The JTLB is organized as 16 pairs of even and odd entries

containing pages that range in size from 4-Kbytes (or 1-

Kbyte) to 256-Mbytes into the 4-Gbyte physical address

space. By default, the minimum page size is normally 4-

Kbytes on the 4KEc core; as a build time option, it is

possible to specify a minimum page size of 1-Kbyte.

The JTLB is organized in page pairs to minimize the

overall size. Each tag entry corresponds to 2 data entries:

an even page entryand an odd page entry. The highest order

virtual address bit not participating in the tag comparison is

used to determine which of the data entries is used. Since

page size can vary on a page-pair basis, the determination

of which address bits participate in the comparison and

which bit is used to make the even-odd determination is

decided dynamically during the TLB look-up.

Instruction TLB (ITLB)

The ITLB is a small 4-entry, fully associative TLB

dedicated to performing translations for the instruction

stream. The ITLB only maps minimum sized pages/

subpages. The minimum page size is either 1-Kbyte or 4-

Kbyte, depending on the PageGrain and Conﬁg3 registers.

The ITLB is managed by hardware and is transparent to

software. The larger JTLB is used as a backing store for the

ITLB. If a fetch address cannot be translated by the ITLB,

the JTLB is used to attempt to translate it in the following

clock cycle. If successful, the translation information is

copied into the ITLB for future use. There is a two cycle

ITLB miss penalty.

Data TLB (DTLB)

The DTLB is a small 4-entry, fully associative TLB

dedicated to performing translations for loads and stores.

Similar to the ITLB, the DTLB only maps either 1-Kbyte

or 4-Kbyte pages/subpages depending on the PageGrain

and Conﬁg3 registers.

The DTLB is managed by hardware and is transparent to

software. The larger JTLB is used as a backing store for the

DTLB. The JTLB is looked up in parallel with the DTLB

to minimize the DTLB miss penalty. If the JTLB

translation is successful, the translation information is

copied into the DTLB for future use. There is a one cycle

DTLB miss penalty.

Virtual-to-Physical Address Translation

Converting a virtual address toa physical address begins by

comparing the virtual address from the processor with the

virtual addresses in the TLB; there is a match when the

Instruction

Address

Calculator

ITLB

DTLB

Data

Address

Calculator

Comparator

Instruction

Cache

Tag RAM

Data

Cache

RAM

Virtual Address

Instruction

Hit/Miss

Data

Hit/Miss

JTLB

IVA

Entry

DVA

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