2.1. CONTROL INFORMATION 11
Sections containing control information are organized in the same way on
Turing, Volta, Pascal and Maxwell. Each section contains 6 fields, organized
as follows:
Width (bits) 4 6 3 3 1 4
Meaning Reuse Wait Read Write Yield Stall
flags barrier barrier barrier flag cycles
mask index index
Fields have the following meaning:
Reuse flags. Each hardware thread on Turing, Volta, Pascal and Maxwell
has a 2-way associative Content-Addressable Memory (CAM) for each of the
four conceptual source registers operand positions. This memory is intended
to allow data reuse between instructions without accessing any register ports:
this relieves pressure on the register file, and helps reducing register bank con-
flicts (we discuss register bank conflicts at length in Section 3.5.1). Reuse flags
control this mechanism as follows: an instruction may flag for saving into the
reuse set any combination of up to its first four arguments. Each instruction
will attempt to service register reads for its first 4 arguments from the respec-
tive reuse slots before resorting to loading values via register file ports. E.g.,
if the last two reuse-saved registers in the second instruction source operand
position were R98 and R99, either of those registers may be used in the sec-
ond position of instructions without contributing to register bank conflicts.
The four bits in the reuse flags map the first to fourth source operands with
the least to most significant bits, respectively.
Wait barrier mask; Read/Write barrier index. While most instructions
have fixed latency and can be statically scheduled by the assembler, instruc-
tions involving memory and shared resources typically have variable latency.
Turing, Volta, Pascal and Maxwell use dependency barriers to track the com-
pletion of variable-latency instructions and resolve data hazards. When a
variable-latency instruction writes to a register, the assembler associates it to
one of the 6 available barriers by setting the corresponding write barrier num-
ber field. When a later instruction consumes that register, the assembler marks
the instruction as waiting on that barrier by setting the bit corresponding to
that barrier in the wait barrier mask. The hardware will stall the later instruc-
tion until the results of the earlier one are available. An instruction may wait
on multiple barriers, which explains why the wait barrier mask is a bitmask,
not an index.
Read dependency barriers. Read dependency barriers serve to protect
against write-after-read hazards. Unbuffered instructions that write the con-
tents of registers to memory need the registers to remain unchanged during
the operation. To guarantee that, the assembler associates them to a barrier
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