使用SystemVerilog进行RTL综合：打破仅用于验证的误解

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"这篇文档揭示了一个普遍误解，即SystemVerilog仅用于验证，而实际上它也可用于编写可综合的RTL代码。文档详细介绍了如何利用SystemVerilog的特性在ASIC和FPGA设计中实现高效的综合，特别提到了Synopsys的Design Compiler (DC)和Synplify-Pro工具的运用。" SystemVerilog是一种强大的硬件描述语言，最初的设计目标之一就是提供更准确、更简洁的复杂硬件设计模型，以支持综合。尽管SystemVerilog在验证领域广泛应用，但它的功能远不止于此。本文档旨在打破SystemVerilog只适用于验证的误区，展示了其在实现ASIC和FPGA设计时的合成潜力。 SystemVerilog的合成子集包含了一系列可被综合工具理解的特性，比如类、接口、多态、位操作以及更复杂的数据结构。这些特性使得设计者能用更少的代码来表示复杂的逻辑，从而降低潜在的设计错误，并在综合过程中实现高质量的结果（Quality of Results，QoR）。 Design Compiler (DC) 和 Synplify-Pro 是Synopsys公司推出的两款重要的综合工具。DC是业界广泛使用的高级综合工具，能处理复杂的SystemVerilog代码，优化设计并生成适合流片的门级网表。Synplify-Pro则专为FPGA设计提供了高效的综合解决方案，同样支持SystemVerilog，使得开发者可以在FPGA设计中充分利用SystemVerilog的优势。通过深入研究SystemVerilog的合成子集，工程师可以学习如何有效利用高级语言特性，例如任务和函数，以及非阻塞赋值，来创建更加模块化和可重用的RTL代码。此外，SystemVerilog的包和接口机制可以帮助设计者更好地组织和管理代码，提高代码复用性和可维护性。对于目标受众——参与RTL设计和综合的工程师来说，理解并掌握这些技巧至关重要，因为他们可以借此提升设计效率，减少调试时间，并且在满足性能、面积和时序约束的同时，提高设计的可预测性和可靠性。这篇文档将帮助工程师拓展对SystemVerilog的理解，不仅限于验证，而是将其作为强大的设计工具，应用于ASIC和FPGA的综合流程中，实现更高效、更可靠的硬件设计。

SNUG Silicon Valley 2013 8 Synthesizing SystemVerilog

Array copy assignments require that the number of dimensions and the number of elements in each

dimension be identical on both sides of the assignment. The number of bits of each element must also be

the same size and of compatible data types. Array copy assignments are synthesizable, and can

significantly reduce the complexity of design code for moving blocks of data from one array to another.

2.5.3 Assigning value lists to arrays

All or multiple elements of an array can be assigned using a list of values, enclosed in ’{ }. The list can

contain values for an individual array element, or a default value for the entire array.

logic [7:0] a, b, c;

logic [7:0] d_array [0:3]; // array with 4 32-bit elements

always_ff @(posedge clock or negedge rstN)

if (!rstN) d_array <= ’{default:0}; // reset all elements of the array

else d_array <= ’{8’h00, c, b, a}; // load the array

Array lists are synthesizable. The number of array dimensions and the number of values in the array list

must be identical. The number of bits of each element must also be the same size as the values in the list.

2.5.4 Passing arrays through module ports and to tasks and functions

The ability to assign to multiple elements of an array also makes it possible to use arrays as module ports

or task/function arguments. The following example defines a user-defined type that represents a 8x256 2-

dimensional array of 32-bit elements, and then passes that array to and from a function, and through

module ports. Section 2.6 discusses user-defined types in more detail, and section 4.1 discusses the

appropriate place to define user-defined types.

typedef logic [31:0] d_array_t [0:7][0:255];

module block_data (input d_array_t d_in, // input is an array

output d_array_t q_out, // output is an array

input logic clock, rstN);

function d_array_t transform (input d_array_t d); // input is an array

// ... perform operations on all elements of d

return d; // return is an array

endfunction

always_ff @(posedge clock or negedge rstN)

if (!rstN) q_out <= ’{default:0}; // reset entire q_out array

else q_out <= transform(d_in); // transform and store entire array

endmodule

Note that SystemVerilog requires that the values passed through an array port or task/function argument

have the same number of dimensions, and that each element be the same vector size and a compatible type.

2.5.5 Array query system functions

SystemVerilog provides a number of special system functions that make it easier to manipulate an array

without hard coding the size of the array. The synthesizable array query functions are:

$left(),

$right(), $low(), $high(), $increment(), $size(), $dimensions(), and

$unpacked_dimensions(). Following is an example of using some of these functions:

SNUG Silicon Valley 2013 9 Synthesizing SystemVerilog

typedef logic [31:0] d_array_t [0:15][0:15];

function d_array_t transform (input d_array_t d);

for (int i = $low(d,1); i <= $high(d,1); i++) begin: outer_loop

for (int j = $low(d,2); j <= $high(d,2); j++) begin: inner_loop

// ... perform some sort of operation on each element of d

end: inner_loop

end: outer_loop

return d; // function return is an array

endfunction

Note: This example could be significantly simplified by using a foreach loop. Unfortunately, foreach is

not supported by DC or Synplify-Pro. See section 12.2 for more details on

foreach loops.

2.5.6 Non-synthesizable array enhancements

SystemVerilog extends Verilog arrays in several other ways that are not synthesizable. These

enhancements include a

foreach array iterator loop, array operation functions, array locator functions,

array sorting functions, and array bit-stream casting.

2.6 User-defined types

The original Verilog language only had built-in data types. SystemVerilog allows design and verification

engineers to create new, user-defined data types. Both variables and nets can be declared as user-defined

types. If neither the

var or a net type keyword is specified, then user-defined types are assumed to be

variables. The synthesizable user-defined types are:

• enum — variables or nets with an enumerated list of legal values — see section 2.6.1

• struct — a structure comprising multiple nets or variables — see section 2.6.2

• union — a variable that can represent different types at different times — see section 2.6.3

•

typedef — type definitions — see section 2.6.4

2.6.1 Enumerated types

Enumerated types allow variables and nets to be defined with a specific set of named values. Only the

synthesizable aspects of enumerated types are presented in this paper. The basic syntax for declaring an

enumerated type is:

// a variable that has 3 legal values

enum {WAITE, LOAD, DONE} State;

Enumerated types have a base data type, which, by default, is int (a 2-state, 32-bit type). In the example

above,

State is an int type, and WAITE, LOAD and DONE will have 32-bit int values. The labels in the

enumerated list are constants that have an associated logic value. By default, the first label in the list has a

logic value of 0, and each subsequent label is incremented by one. Thus, in the example above,

WAITE is 0,

LOAD is 1, and DONE is 2.

Designers can specify an explicit base type, allowing enumerated types to more specifically model

hardware. Designers can specify explicit values for any or all labels in the enumerated list. An example is:

// Two 3-bit, 4-state enumerated variables with one-hot values

enum logic [2:0] {WAITE = 3’b001,

LOAD = 3’b010,

DONE = 3’b100} State, NextState;

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使用SystemVerilog进行RTL综合：打破仅用于验证的误解

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