STM32F070系列ARM Cortex-M0 MCU数据手册：特性与功能详述

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"STM32F070CB/STM32F070RB/STM32F070C6/STM32F070F6是基于ARM Cortex-M0内核的32位微控制器数据手册，具有从32KB到128KB的闪存，USB FS 2.0接口，11个定时器，ADC和多种通信接口，工作电压范围在2.4V至3.6V之间。" STM32F070系列是意法半导体（STMicroelectronics）推出的一系列高性能、低功耗的微控制器，主要应用于嵌入式系统设计。这些芯片基于ARM公司的Cortex-M0架构，提供了高效的处理能力。Cortex-M0是ARM针对微控制器市场设计的一种精简指令集（RISC）处理器核心，其频率可高达48MHz，确保了快速响应和高效运算。内存方面，STM32F070系列提供了32KB到128KB的闪存存储空间，用于存放程序代码和配置数据。同时，它配备了6KB到16KB的SRAM，并且带有硬件奇偶校验功能，增强了数据的稳定性和可靠性。CRC计算单元则可以对数据进行校验，防止传输或存储中的错误。电源管理是STM32F070系列的重要特性，它支持2.4V至3.6V的数字和I/O电源，以及2.4V至3.6V的模拟电源。设备具备上电/掉电复位（POR/PDR）功能，以及睡眠、停止和待机等低功耗模式，以适应不同应用场景的需求。时钟管理方面，STM32F070具备多种时钟源，包括4MHz到32MHz的晶体振荡器，一个用于RTC的32kHz振荡器，一个内部8MHz RC振荡器（可倍频至64MHz），以及一个40kHz的内部RC振荡器。丰富的时钟选项确保了系统在各种条件下都能正常运行。该系列微控制器提供多达51个快速I/O引脚，所有I/O都可以映射到外部中断向量，其中部分I/O支持5V耐压能力。此外，它还配备了一个5通道DMA控制器，能有效提高数据传输效率。 STM32F070集成了一个12位ADC，转换时间仅为1.0μs，支持最多16个输入通道，测量范围为0到3.6V。ADC还可以使用独立的2.4V至3.6V模拟电源，确保了高精度的模拟信号处理。另外，还包括一个带有闹钟和周期性唤醒功能的日历RTC，以及11个定时器，其中一个为16位高级定时器，支持多种定时和计数任务。通信接口也是STM32F070的一大亮点，它支持多种标准通信协议，如UART, SPI, I2C等，方便与各种外设和传感器进行连接。USB FS 2.0接口使得设备能够轻松接入USB系统，实现数据传输和设备控制。 STM32F070系列微控制器是适用于各种嵌入式应用的理想选择，其强大的处理能力、丰富的外设和灵活的电源管理方案，使其能够在物联网、消费电子、工业控制等领域发挥重要作用。

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Functional overview STM32F070CB/RB/C6/F6

14/83 DocID027114 Rev 3

3.5.4 Low-power modes

The STM32F070CB/RB/C6/F6 microcontrollers support three low-power modes to achieve

the best compromise between low power consumption, short startup time and available

wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves very low power consumption while retaining the content of SRAM

and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the

HSE crystal oscillators are disabled. The voltage regulator can also be put either in

normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line

source can be one of the 16 external lines and RTC.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the RTC

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pins, or an RTC event occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

3.6 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the application to configure the frequency of the AHB and the APB

domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

Functional overview STM32F070CB/RB/C6/F6

16/83 DocID027114 Rev 3

3.8 Direct memory access controller (DMA)

The 5-channel general-purpose DMA manages memory-to-memory, peripheral-to-memory

and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code

intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, all TIMx timers (except

TIM14) and ADC.

3.9 Interrupts and events

3.9.1 Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to

32 maskable interrupt channels (not including the 16 interrupt lines of Cortex

-M0) and 4

priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

3.9.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 32 edge detector lines used to generate

interrupt/event requests and wake-up the system. Each line can be independently

configured to select the trigger event (rising edge, falling edge, both) and can be masked

independently. A pending register maintains the status of the interrupt requests. The EXTI

can detect an external line with a pulse width shorter than the internal clock period. Up to 51

GPIOs can be connected to the 16 external interrupt lines.

DocID027114 Rev 3 17/83

STM32F070CB/RB/C6/F6 Functional overview

3.10 Analog to digital converter (ADC)

The 12-bit analog to digital converter has up to 16 external and two internal (temperature

sensor, voltage reference measurement) channels and performs conversions in single-shot

or scan modes. In scan mode, automatic conversion is performed on a selected group of

analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

3.10.1 Temperature sensor

The temperature sensor (TS) generates a voltage V

SENSE

that varies linearly with

temperature.

The temperature sensor is internally connected to the ADC_IN16 input channel which is

used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall

accuracy of the temperature measurement. As the offset of the temperature sensor varies

from chip to chip due to process variation, the uncalibrated internal temperature sensor is

suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is

individually factory-calibrated by ST. The temperature sensor factory calibration data are

stored by ST in the system memory area, accessible in read-only mode.

3.10.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

) provides a stable (bandgap) voltage output for the

ADC. V

REFINT

is internally connected to the ADC_IN17 input channel. The precise voltage

of V

REFINT

is individually measured for each part by ST during production test and stored in

the system memory area. It is accessible in read-only mode.

Table 2. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS ADC raw data acquired at a

temperature of 30 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

0x1FFF F7B8 - 0x1FFF F7B9

Table 3. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at a

temperature of 30 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

0x1FFF F7BA - 0x1FFF F7BB

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