Intel
®
Xeon
TM
Processor MP
16 Datasheet
Care must be taken in the board design to ensure that the voltage provided to the processor remains
within the specifications listed in Table 6. Failure to do so can result in timing violations or reduced
lifetime of the component. For further information and guidelines, refer to the appropriate platform
design guidelines.
2.3.1 V
CC
Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and maintain a low interconnect resistance from the regulator (or voltage regulator pins) to the 603-
pin socket. Bulk decoupling may be provided on the voltage regulation module (VRM) to meet the
needs of large current swings. The power delivery path must be capable of delivering enough
current while maintaining the required tolerances (defined in Table 6). For further information
regarding power delivery, decoupling, and layout guidelines, refer to the appropriate platform
design guidelines.
2.3.2 System Bus AGTL+ Decoupling
The processor integrates a portion of the required high frequency decoupling capacitance on the
processor package. However, additional high frequency capacitance must be added to the system
board to properly decouple the return currents from the system bus. Bulk decoupling must also be
provided by the system board for proper AGTL+ bus operation. Decoupling guidelines are
described in the appropriate platform design guidelines.
2.4 System Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the Intel Xeon processor MP core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will have a maximum
ratio set during manufacturing. Platforms will use the ratio-setting pins, as in previous generation
Pentium III Xeon processors, to configure the processor to run at its maximum ratio, or lower. This
feature is provided to ensure that multiprocessing systems, which typically are not fully populated
with processors at time of purchase, may be upgraded at a later date and have all processors run at
the same core frequency.
Clock multiplying within the processor is provided by the internal PLL, which requires a constant
frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC
specifications for the BCLK[1:0] inputs are provided in Table 7 and Table 13, respectively. These
specifications must be met while also meeting signal integrity requirements as outlined in Chapter
3.0. Unlike previous processors, Intel Xeon processors utilize differential clocks. Details regarding
BCLK[1:0] driver specifications are provided in the CK00 Clock Synthesizer/Driver Design
Guidelines document.
The BCLK[1:0] inputs directly control the operating speed of the system bus interface. The
processor core frequency must be configured during Reset by using the A20M#, IGNNE#,
LINT[1]/NMI, and LINT[0]/INTR pins (see Table 2). The value on these pins during Reset
determines the multiplier that the Phase Lock Loop (PLL) will use for the internal core clock.
Production units of the processor are limited to their maximum bus-to-core ratio and only the
maximum or lower ratios are supported. If a ratio higher than the maximum is chosen, the
processor will default to the maximum ratio. The maximum ratio for each processor is equal to the
core frequency divided by the bus frequency marked on the processor.
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