Intel至强处理器MP：1.40-1.60GHz，高性能服务器核心

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“主频为1.40 GHz、1.50 GHz和1.60 GHz的英特尔64位至强处理器MP数据表” 本文将详细介绍基于Intel NetBurst微架构的Intel至强处理器MP系列，这是一个专为高性能企业级和电子商务服务器应用设计的处理器家族。这些处理器具有与先前Intel IA-32架构处理器的二进制兼容性，并引入了Hyper-Threading技术，以提升多处理服务器平台的性能。 1. **产品特性** - **频率与性能**：Intel Xeon Processor MP提供1.40 GHz、1.50 GHz和1.60 GHz三种主频选项，能够在多处理器系统中实现卓越的性能，尤其适合运行在Windows 2000 Server、Linux、Netware和UNIX等先进操作系统上的企业服务器应用。 - **扩展性**：处理器可扩展至四个或更多处理器，以满足大型多处理器系统的需求，为关键任务应用提供强大支持。 - **技术集成**：Intel的NetBurst架构优化了处理器性能，同时引入的Hyper-Threading技术允许单个物理核心同时处理多个线程，显著提升了处理器的并行处理能力。 - **缓存配置**：第一代至强处理器MP配备256KB二级高速缓存和512KB或1MB三级高速缓存，而更新的版本则拥有512KB二级高速缓存和1MB、2MB或4MB的三级高速缓存，提供了更高级别的数据存储和访问速度。 - **制程技术**：早期的处理器采用0.18微米制程，而较新的处理器则采用更为先进的0.13微米制程，这不仅提高了晶体管密度，还降低了功耗和发热量。 2. **系统管理和可靠性** - **增强系统管理**：Intel Xeon Processor MP具备一系列先进功能，简化了系统管理，包括硬件级别的故障检测和恢复机制，以及对远程监控和维护的支持，确保了系统的高可用性和稳定性。 - **系统稳定性**：通过优化设计，这些处理器能够满足企业级环境中对持续运行时间的要求，最大化系统无故障时间。 - **配置灵活性**：针对不同的企业需求，提供了不同级别的三级高速缓存大小，以优化不同工作负载的性能表现。 Intel Xeon Processor MP系列处理器凭借其高性能、高扩展性和优秀的系统管理特性，成为了企业级服务器和关键任务应用的理想选择。它们的高性能表现、多处理器支持以及Hyper-Threading技术的应用，确保了在各种计算密集型和并发任务中的高效处理。结合与多种操作系统兼容的特性，这些处理器能够为企业构建出稳定、高效且易于管理的服务器环境。

Intel

Xeon

Processor MP

16 Datasheet

Care must be taken in the board design to ensure that the voltage provided to the processor remains

within the specifications listed in Table 6. Failure to do so can result in timing violations or reduced

lifetime of the component. For further information and guidelines, refer to the appropriate platform

design guidelines.

2.3.1 V

Decoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and maintain a low interconnect resistance from the regulator (or voltage regulator pins) to the 603-

pin socket. Bulk decoupling may be provided on the voltage regulation module (VRM) to meet the

needs of large current swings. The power delivery path must be capable of delivering enough

current while maintaining the required tolerances (defined in Table 6). For further information

regarding power delivery, decoupling, and layout guidelines, refer to the appropriate platform

design guidelines.

2.3.2 System Bus AGTL+ Decoupling

The processor integrates a portion of the required high frequency decoupling capacitance on the

processor package. However, additional high frequency capacitance must be added to the system

board to properly decouple the return currents from the system bus. Bulk decoupling must also be

provided by the system board for proper AGTL+ bus operation. Decoupling guidelines are

described in the appropriate platform design guidelines.

2.4 System Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the

processor. As in previous generation processors, the Intel Xeon processor MP core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will have a maximum

ratio set during manufacturing. Platforms will use the ratio-setting pins, as in previous generation

Pentium III Xeon processors, to configure the processor to run at its maximum ratio, or lower. This

feature is provided to ensure that multiprocessing systems, which typically are not fully populated

with processors at time of purchase, may be upgraded at a later date and have all processors run at

the same core frequency.

Clock multiplying within the processor is provided by the internal PLL, which requires a constant

frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC

specifications for the BCLK[1:0] inputs are provided in Table 7 and Table 13, respectively. These

specifications must be met while also meeting signal integrity requirements as outlined in Chapter

3.0. Unlike previous processors, Intel Xeon processors utilize differential clocks. Details regarding

BCLK[1:0] driver specifications are provided in the CK00 Clock Synthesizer/Driver Design

Guidelines document.

The BCLK[1:0] inputs directly control the operating speed of the system bus interface. The

processor core frequency must be configured during Reset by using the A20M#, IGNNE#,

LINT[1]/NMI, and LINT[0]/INTR pins (see Table 2). The value on these pins during Reset

determines the multiplier that the Phase Lock Loop (PLL) will use for the internal core clock.

Production units of the processor are limited to their maximum bus-to-core ratio and only the

maximum or lower ratios are supported. If a ratio higher than the maximum is chosen, the

processor will default to the maximum ratio. The maximum ratio for each processor is equal to the

core frequency divided by the bus frequency marked on the processor.

Intel

Xeon

Processor MP

Datasheet 19

NOTES:

1. These multipliers are supported on C stepping processors.

2. Refer to the Intel

Xeon

Processor MP Specification Update for processor stepping details.

2.4.3 Mixing Processors

Mixing processors operating at different internal clock frequencies is not supported and has not

been validated by Intel. Not all operating systems can support multiple processors with mixed

frequencies. Intel does not support or validate operation of processors with different cache sizes.

Intel only supports and validates multi-processor configurations where all processors operate with

the same system bus, core frequencies, VID settings, and have the same internal cache sizes.

Mixing processors of different steppings but the same model (as per CPUID instruction) is

supported. Details on CPUID are provided in the IA32 Architecture Software Developer’s Manual

and the IntelProcessor Identification and the CPUID Instruction application note.

2.5 Voltage Identification

The VID specification for Intel Xeon processor MP is different from that of previous generations

and is supported by the VRM 9.1 DC-DC Convertor Design Guidelines. The voltage set by the VID

pins is the maximum voltage allowed by the processor. A minimum voltage is provided in Table 6

and changes with frequency. This allows processors running at a higher frequency to have a relaxed

minimum voltage specification. The specifications have been set such that one voltage regulator

can work with all supported frequencies.

The processor uses five voltage identification pins, VID[4:0], to support automatic selection of

power supply voltages. Table 3 specifies the voltage level corresponding to the state of VID[4:0]. A

‘1’ in this table refers to a high voltage and a ‘0’ refers to low voltage level. The definition

Table 2. Core Frequency to System Bus Multiplier Configuration

Multiplier for System Bus-

to-Core Frequency

Core Frequency

LINT[1]/

NMI

A20M# IGNNE#

LINT[0]/

INTR

Notes

1/8 800MHz HHHH

1/9 900 MHz H H H L

1/23 2.30 GHz H H H L

1/10 1.00 GHz H H L H

1/11 1.10 GHz H H L L

1/12 1.20 GHz H L H H

1/13 1.30 GHz H L H L

1/14 1.40 GHz H L L H 1

1/15 1.50 GHz H L L L 1

1/16 1.60 GHz L H H H 1

1/17 1.70 GHz L H H L

1/18 1.80 GHz L H L H

1/19 1.90 GHz L H L L

1/20 2.00 GHz L L H H

1/21 2.10 GHz L L H L

1/22 2.20 GHz L L L H

1/24 2.40 GHz L L L L

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