TI DS90UR907Q-Q1：FPD-Link至FPD-LinkII转换器详解

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TI的DS90UR907Q-Q1是一款高性能的FPD-Link转换器，它专为解决显示器链路通信问题而设计。这款器件支持5-65MHz频段（对应于140Mbps至1.82Gbps的数据传输速率），是将传统的FPD-Link接口升级到更高级别的FPD-LinkII的解决方案。DS90UR907Q的主要特性包括： 1. 数据与控制信号转换：它能够处理4个低压差分信令（LVDS）数据/控制流，以及1个LVDS时钟对，将这些信号从FPD-Link转换为FPD-LinkII的单线高速串行接口，从而提高传输效率并减少电缆长度带来的STP（树形协议）时钟和数据同步问题。 2. 简化系统设计：通过内置的全速自检功能（BIST），DS90UR907Q可以检测线路状况，减少外部连接的复杂性和成本，同时简化PCB布局，降低功耗和电磁干扰（EMI）。 3. 集成I2C兼容性：该转换器提供I2C兼容的串行控制总线接口，方便与控制器和其他设备的通信，进一步增强了系统的灵活性。 4. DC均衡编码与信号增强：DS90UR907Q包含随机发生器/扰频器和DC均衡器，用于优化LVDS数据流的质量，以及对LVDS时钟对进行电平调整，确保信号的稳定传输。 5. 视频功能支持：它具备视频点播（VOD）和可调去加重功能，能有效处理FPD-Link内高达24位的视频信号，提供优质的显示性能。 6. 电源管理：在断电模式下，DS90UR907Q能够显著减少功耗，延长电池寿命或在低功耗应用中提供高效能。 DS90UR907Q-Q1是一款强大的FPD-Link到FPD-LinkII转换器，它在提升数据传输速度、降低信号复杂性、增强系统稳定性以及扩展视频处理能力等方面具有显著优势，广泛适用于需要高效、稳定显示器连接的电子设备中。

DS90UR907Q-Q1

ZHCSB28F –SEPTEMBER 2009–REVISED APRIL 2013

www.ti.com.cn

DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)(2)(3)

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

LVCMOS INPUT DC SPECIFICATIONS

DDIO

= 3.0 to 3.6V 2.2 V

DDIO

High Level Input Voltage

DDIO

= 1.71 to 1.89V 0.65* V

DDIO

= 3.0 to 3.6V GND 0.8 V

PDB,

Low Level Input Voltage VODSEL,

0.35*

DDIO

= 1.71 to 1.89V GND V

MAPSEL,

DDIO

CONFIG[1:0],

DDIO

= 3.0

BISTEN

−15 ±1 +15 μA

to 3.6V

Input Current V

= 0V or V

DDIO

= 1.7

−15 ±1 +15 μA

to 1.89V

FPD-LINK LVDS RECEIVER DC SPECIFICATIONS

Differential Threshold High

+100

Voltage

Differential Threshold Low

= 1.2V, Figure 2 −100

Voltage

RxIN[3:0]+/-,

Differential Input Voltage

| 200 600 mV

RxCLKIN+/-,

Swing

DDIO

= 3.3V 0 1.2 2.4

Common Mode Voltage V

DDIO

= 1.8V 0 1.2 1.55

Input Current −15 ±1 +15 μA

FPD-LINK II LVDS DRIVER DC SPECIFICATIONS

VODSEL = 0 ±225 ±300 ±375

Differential Output Voltage mV

= 100Ω,

VODSEL = 1 ±350 ±450 ±550

De-emph = disabled,

VODSEL = 0 600 mVp-p

Differential Output Voltage

Figure 4

ODp-p

(DOUT+) – (DOUT-)

VODSEL = 1 900 mVp-p

= 100Ω, De-emph = disabled,

ΔV

Output Voltage Unbalance 1 50 mV

VODSEL = L

Offset Voltage – Single- VODSEL = 0 1.65 V

= 100Ω,

DOUT+,

ended

De-emph = disabled

DOUT-

VODSEL = 1 1.575 V

At TP A & B, Figure 3

Offset Voltage Unbalance

ΔV

Single-ended R

= 100Ω, De-emph = disabled 1 mV

At TP A & B, Figure 3

DOUT+/- = 0V,

Output Short Circuit Current VODSEL = 0 −35 mA

De-emph = disabled

Internal Termination 80

120 Ω

Resistor

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) Typical values represent most likely parametric norms at V

= 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at

the time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground

except VOD, ΔVOD, VTH and VTL which are differential voltages.

DS90UR907Q-Q1

www.ti.com.cn

ZHCSB28F –SEPTEMBER 2009–REVISED APRIL 2013

DC Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)(2)(3)

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units

SUPPLY CURRENT

DDT1

Checker Board V

= 1.89V All V

pins 80 90 mA

Pattern,

DDIO

= 1.89V 3 5 mA

De-emph = 3 kΩ,

DDIOT1

DDIO

VODSEL = H,

DDIO

= 3.6V 10 13 mA

Supply Current

Figure 11

(includes load current)

DDT2

Checker Board V

= 1.89V All V

pins 75 85 mA

= 100Ω, f = 65MHz

Pattern,

DDIO

= 1.89V 3 5 mA

De-emph = 6 kΩ,

DDIOT2

DDIO

VODSEL = L,

DDIO

= 3.6V 10 13 mA

Figure 11

DDZ

= 1.89V All V

pins 60 1000 µA

PDB = 0V , (All other

Supply Current Power-down LVCMOS Inputs = V

DDIO

= 1.89V 0.5 10 µA

DDIOZ

DDIO

0V)

DDIO

= 3.6V 1 30 µA

Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

FPD-LINK LVDS INPUT

RSP0

Receiver Strobe Position-bit 0 0.66 1.10 1.54 ns

RSP1

Receiver Strobe Position-bit 1 2.86 3.30 3.74 ns

RSP2

Receiver Strobe Position-bit 2 5.05 5.50 5.93 ns

RxCLKIN = 65 MHz,

RSP3

Receiver Strobe Position-bit 3 RxIN[3:0] 7.25 7.70 8.13 ns

Figure 6

RSP4

Receiver Strobe Position-bit 4 9.45 9.90 10.33 ns

RSP5

Receiver Strobe Position-bit 5 11.65 12.10 12.53 ns

RSP6

Receiver Strobe Position-bit 6 13.85 14.30 14.73 ns

FPD-LINK II LVDS OUTPUT

HLT

Output Low-to-High Transition R

= 100Ω, De-emphasis = disabled, VODSEL = 0 200 ps

Time, Figure 5

= 100Ω, De-emphasis = disabled, VODSEL = 1 200 ps

HLT

Output High-to-Low Transition R

= 100Ω, De-emphasis = disabled, VODSEL = 0 200 ps

Time, Figure 5

= 100Ω, De-emphasis = disabled, VODSEL = 1 200 ps

XZD

Ouput Active to OFF Delay,

5 15 ns

Figure 8

PLD

PLL Lock Time, Figure 7 R

= 100Ω

(1)

1.5 10 ms

Delay - Latency, Figure 9 R

= 100Ω 140*T 145*T ns

DJIT

Output Total Jitter, R

= 100Ω, De-Emph = disabled,

0.26 UI

Figure 10 RANDOM pattern, RxCLKIN = 43 & 65 MHz

(2)

STXBW

Jitter Transfer RxCLKIN = 43 MHz 2.2

MHz

Function -3 dB Bandwidth

(3) (4)

RxCLKIN = 65 MHz 3

STX

Jitter Transfer RxCLKIN = 43 MHz 1

Function Peaking

(3)(4)

RxCLKIN = 65 MHz 1

(1) t

PLD

is the time required by the device to obtain lock when exiting power-down state with an active RxCLKIN.

(2) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*RxCLKIN). The UI scales with RxCLKIN frequency.

(3) Specification is ensured by characterization and is not tested in production.

(4) Specification is ensured by design and is not tested in production.

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