AR9220：2.4/5GHz双频MIMO无线网卡芯片MINPCI接口详解

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AR9220手册提供了关于Atheros公司生产的高性能双频（2.4GHz和5.8GHz）802.11n无线局域网（WLAN）芯片的详细信息。这款单芯片解决方案，集成了MAC（媒体接入控制）控制器、基带处理器、模拟到数字和数字到模拟转换器（ADC/DAC），专为要求高数据传输速率、稳定链接质量和范围的无线站应用设计。它支持2x2 MIMO（多输入多输出）配置，旨在提供卓越的无线性能。 AR9220的核心特点包括： 1. **集成度高**：作为一个单一芯片解决方案，AR9220实现了系统级的集成，减少了外部组件的需求，简化了设计过程，提高了系统的稳定性和可靠性。 2. **2.4GHz和5GHz频段支持**：适用于广泛的无线网络环境，能够适应不同场景下的需求，如家庭、办公场所或商业空间。 3. **802.11n标准兼容**：遵循Wi-Fi联盟的802.11n标准，该标准定义了高速无线通信技术，支持MIMO技术，提升了数据传输速度。 4. **MIMO配置**：2x2 MIMO允许两个独立的数据流同时在两个天线之间传输，从而实现更高的吞吐量和更好的抗干扰能力，提升无线网络的效率。 5. **MAC和基带处理器**：内置的多协议MAC确保了高效的数据包处理和无线网络管理，而基带处理器则负责无线信号的编码和解码，确保了数据的准确传输。 6. **模拟与数字转换**：ADC和DAC确保了无线信号的高质量转换，这对于接收和发送信号至关重要。 7. **专利技术**：手册中提到的诸如Atheros SST（信号持续技术）、Air is Cleaner at 5-GHz、XSPAN、Wireless Future Unleashed Now以及5-UP等都是Atheros公司的创新技术，旨在优化无线信号的性能和稳定性。 8. **商标和版权信息**：手册强调了Atheros公司的各种商标和版权，表明其对知识产权的重视，并提醒用户可能的后续更新和规范变更。 9. **接口**：AR9220支持MINPCI接口，这是一种小型PCI扩展槽，便于在各种计算机硬件平台上使用。 AR9220手册为开发人员、工程师和系统集成者提供了全面的技术指南，帮助他们了解如何利用这款芯片构建具备强大性能、可靠性和高效能的802.11n无线网络系统。通过深入理解和掌握AR9220的功能和特性，用户可以优化无线网络部署，满足不断增长的无线连接需求。

16 • AR9220 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs Atheros Communications, Inc.

16 • October 2009 COMPANY CONFIDENTIAL

Atheros Communications, Inc. AR9220 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs • 17

COMPANY CONFIDENTIAL October 2009 • 17

3. Medium Access Control (MAC)

The MAC consists of the following major

functional blocks: 10 queue control units

(QCUs), 10 distributed coordination function

(DCF) control units (DCUs), a single DMA Rx

unit (DRU), and a single protocol control unit

(PCU). See Figure 3-1.

3.1 Overview

The MAC block supports full bus-mastering

descriptor-based scatter/gather DMA. Frame

transmission begins with the QCUs. QCUs

manage the DMA of frame data from the host

through the PCI interface, and determine

when a frame is available for transmission.

Each QCU targets exactly one DCU. Ready

frames are passed from a QCU to its targeted

DCU. The DCU manages the enhanced

distributed coordination function (EDCF)

channel access procedure on behalf of the

QCUs associated with it.

Functionality of the MAC block includes:

■ Tx frame data transfer from the host to the

radio block using the PCI bus

■ Rx frame data transfer from the radio block

to host using the PCI bus

■ Register access to all AR9220 registers

■ Interrupt generation and reporting

■ Sleep-mode (power-down) sequencing

■ Miscellaneous error and status reporting

functions

Once the DCU gains access to the channel, it

passes the frame to the PCU, which encrypts

the frame and sends it to the baseband logic.

The PCU handles both processing responses to

the transmitted frame, and reporting the

transmission attempt results to the DCU.

Frame reception begins in the PCU, which

receives the incoming frame bitstream from the

digital PHY. The PCU decrypts the frame and

passes it to the DRU, which manages Rx

descriptors and writes the incoming frame data

and status to the host memory through the

PCI interface.

3.2 Descriptor

The MAC is responsible for transferring frames

between the host memory (accessed using the

PCI interface) and the AR9220. For all normal

frame transmit/receive activity, the host

provides a series of descriptors to the MAC,

and the MAC then parses the descriptors and

performs the required set of data transfers.

Figure 3-1. MAC Block Diagram

18 • AR9220 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs Atheros Communications, Inc.

18 • October 2009 COMPANY CONFIDENTIAL

3.3 Descriptor Format

The transmit (Tx) descriptor format contains

24 32-bit words and the receive (Rx) descriptor

13 32-bit words (see Table 3-1).

The first two words of the descriptor point to

the next descriptor in the linked list and to the

data buffer associated with the descriptor.

Other words carry additional control

information that affects how the MAC

processes the frame and its data.

A descriptor is required to be aligned on a

32-bit boundary in host memory, although best

performance is achieved if the descriptor is

aligned on a cache-line boundary. The MAC

uses the final two words to report status

information back to the host. See:

Table Description

Table 3-1 DMA descriptor format

Table 3-2 Tx control descriptor format

(words 2–13)

Table 3-3 Tx status descriptors

(words 14–23)

Table 3-4 Rx control descriptor

(words 2–3)

Table 3-5 Rx status descriptor

(words 4–12)

Table 3-1. DMA Descriptor Format

Word Bits Field Name Description

0 31:0 link_ptr Link pointer. Contains the address of the next descriptor to be used; must

be 32-bit aligned (bits [1:0] must be 0)

1 31:0 buf_ptr Data buffer pointer. Contains the starting address of the data buffer

associated with this descriptor. A Tx data buffer can begin at any byte

address. A Rx data buffer must be aligned on a 32-bit boundary in host

memory, although best performance is achieved if the Rx data buffer is

cache-line aligned.

(Cache-line size varies from system to system.)

2–13 (Tx)

2–3 (Rx)

31:0 Host-to-

DMA engine

control

information

Additional control information is passed from host to DMA engine. The

format of these words varies depending on whether the descriptor is being

used to Tx a frame from host to PCU, or Rx a frame from PCU to host.

(See Table 3-2 on page 19, and Table 3-4 on page 28 for details.)

14–23 (Tx)

4–12 (Rx)

31:0 DMA

completion

status

information

Status information reported by the DMA engine when it has finished

processing a descriptor. As with the control information, the format of the

status information differs between Tx and Rx descriptors.

(See Table 3-3 on page 25, and Table 3-5 on page 28 for details.)

Atheros Communications, Inc. AR9220 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs • 19

COMPANY CONFIDENTIAL October 2009 • 19

The Tx descriptor format for words 2 through

13 is described in Table 3-2.

Table 3-2. Tx Control Descriptor Format (Words 2–13)

Word Bits Field Name Description

2 11:0 frame_length Frame length

Specifies the length, in bytes, of the entire MAC frame, including the frame

check sequence (FCS), initialization vector (IV), and integrity check value

(ICV) fields.

12 vmf Virtual more fragment

If this bit is set, bursting is enabled for this frame. If no burst is in progress, it

initiates a CTS-protected burst if cts_enable is set. If a previous burst is in

progress, it ignores the cts_enable bit and assumes the burst is protected.

13 RES Reserved

14 low_rx_chain When set to 1, indicates that the Rx chain mask switches to low power mode

after transmitting this frame.

15 clear_retry Setting this bit disables the retry bit from being set in the Tx header on a

frame retry (applies to both aggregate and non-aggregate frames).

21:16 tpc_0 Tx power control for series 0

These bits pass unchanged to the baseband, where they are used to control

the transmit power for the frame.

22 rts_enable Request to send (RTS) enable. At most, one of the “rts_enable” and

“cts_enable” bits may be set; it is illegal to set both.

set PCU transmits the frame using the RTS/CTS protocol

clear PCU transmits the frame using the contention/backoff protocol

23 veol Virtual end-of-list flag

When set, indicates that the QCU should act as though the descriptor had a

NULL LinkPtr, even if the LinkPtr is not NULL. Must be valid in the final

descriptor of a frame and must be clear for all other descriptors of the frame.

24 clear_dest_mask Clear destination mask bit flag

If set, instructs the PCU and DCU to clear the destination mask bit at the

index specified by the DestIdx field.

28:25 RES Reserved

29 int_req Interrupt request flag

Set to one by the driver to request that the DMA engine generate an interrupt

upon completion of the frame to which this descriptor belongs.

Note that this field must be valid and identical for all descriptors of the

frame; that is, all descriptors for the frame must have this flag set, or all

descriptors for the frame must have this flag clear.

30 dest_index_valid Destination index valid flag

Specifies whether the contents of the DestIdx field are valid.

31 cts_enable Proceed frame with CTS flag

If set, the PCU first sends a CTS before sending the frame described by the

descriptor. Used for 802.11g and Atheros XR frames to quiet legacy stations

before sending a frame the legacy stations cannot interpret (even at the PHY

level). At most, one of the “rts_enable” and “cts_enable” bits may be set; it is

illegal to set both bits.

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