HCS08 MC9S08DN60系列：8位处理器与嵌入式内存特性
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MC9S08DN60是一款由飞思卡尔(Freescale,现已被NXP收购)生产的8位HCS08微控制器系列中的成员。该系列的特点是其高效能的40-MHz HCS08中央处理器(CPU)，运行在20-MHz总线架构上，扩展了HC08指令集，增加了BGND指令，这使得它在处理速度和功能上有了显著提升。这款微控制器支持多达32个中断或复位源，具备强大的硬件中断管理能力。
内存配置方面，MC9S08DN60提供了60K字节（KB）的闪存，可以实现全电压和温度范围下的读写操作，包括在执行Flash程序时进行编程和擦除的功能。此外，它还内置了2K字节的EEPROM，支持单页8字节或双页4字节的擦除，以及在执行过程中进行的编程和擦除操作，允许用户灵活选择存储方案。随机访问内存(RAM)容量为2K字节，为数据暂存和快速处理提供了支持。
为了优化电池寿命和降低功耗，MC9S08DN60具备两种非常低功耗的停机模式：一种是深度睡眠模式，另一种是减半功率等待模式。还有一个非常低功耗的实时中断模式，适用于运行、等待和停止状态，确保在节能的同时仍能响应关键事件。
时钟源选项丰富，包括内置的XOSC振荡器，可以设置为环路控制Pierce振荡器，频率范围从31.25kHz到38.4kHz或1MHz到16MHz。另外，还有Multi-purpose Clock Generator (MCG)模块，支持PLL和FLL模式，其中FLL具有出色的精度，能达到1.5%的误差，且通过内部温度补偿进行优化。此外，微控制器还配备了一个可调工厂预校准的内部参考时钟，提供高度的时钟稳定性。
MC9S08DN60作为一款高性能、低功耗的微控制器，集成了高效的CPU、大容量存储和多种节能模式，适合于对功耗敏感且对处理能力和存储需求较高的应用场合，如嵌入式系统、工业自动化设备等。它的设计考虑到了广泛的时钟源选择，以适应不同的系统设计需求。
MC9S08DN60 Series Data Sheet, Rev 3
16 Freescale Semiconductor
Section Number Title Page
15.1.3 Block Diagram ................................................................................................................262
15.2 Signal Description..........................................................................................................................264
15.2.1 Detailed Signal Descriptions ...........................................................................................264
15.3 Register Definition .........................................................................................................................268
15.3.1 TPM Status and Control Register (TPMxSC) ................................................................268
15.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................269
15.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................270
15.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................271
15.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................272
15.4 Functional Description...................................................................................................................274
15.4.1 Counter ............................................................................................................................274
15.4.2 Channel Mode Selection .................................................................................................276
15.5 Reset Overview ..............................................................................................................................279
15.5.1 General ............................................................................................................................279
15.5.2 Description of Reset Operation .......................................................................................279
15.6 Interrupts ........................................................................................................................................279
15.6.1 General ............................................................................................................................279
15.6.2 Description of Interrupt Operation ..................................................................................280
15.7 The Differences from TPM v2 to TPM v3.....................................................................................281
Chapter 16
Development Support
16.1 Introduction....................................................................................................................................287
16.1.1 Forcing Active Background ............................................................................................287
16.1.2 Features ...........................................................................................................................288
16.2 Background Debug Controller (BDC) ...........................................................................................288
16.2.1 BKGD Pin Description ...................................................................................................289
16.2.2 Communication Details ..................................................................................................290
16.2.3 BDC Commands .............................................................................................................294
16.2.4 BDC Hardware Breakpoint .............................................................................................296
16.3 On-Chip Debug System (DBG) .....................................................................................................297
16.3.1 Comparators A and B ......................................................................................................297
16.3.2 Bus Capture Information and FIFO Operation ...............................................................297
16.3.3 Change-of-Flow Information ..........................................................................................298
16.3.4 Tag vs. Force Breakpoints and Triggers .........................................................................298
16.3.5 Trigger Modes .................................................................................................................299
16.3.6 Hardware Breakpoints ....................................................................................................301
16.4 Register Definition .........................................................................................................................301
16.4.1 BDC Registers and Control Bits .....................................................................................301
16.4.2 System Background Debug Force Reset Register (SBDFR) ..........................................303
16.4.3 DBG Registers and Control Bits .....................................................................................304
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