"eMMC5.1 JEDEC官方Spec文档原版带目录及协议文档汇总"

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The eMMC5.1 JEDEC official Spec document is a comprehensive guide that outlines the Embedded Multi-Media Card (eMMC) Electrical Standard. This document, officially known as JESD84-B51, is a revision of the previous version JESD84-B50.1 from July 2014, and was released in February 2015 by the JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. The eMMC standard is crucial in defining the electrical interface between embedded memory devices and the host system. It sets the guidelines for the communication protocol, power supply, data transfers, and other important aspects of eMMC technology. This standardization ensures interoperability and compatibility among different eMMC devices, allowing for seamless integration into various electronic systems. The JEDEC standards and publications, including the eMMC5.1 standard, undergo a rigorous review and approval process by the JEDEC Board of Directors and legal counsel. This ensures that the material is accurate, reliable, and in line with industry best practices. The main goal of these standards is to promote the public interest by enabling innovation, reliability, and efficiency in electronic devices. Overall, the eMMC5.1 JEDEC official Spec document is an essential resource for manufacturers, designers, and developers working with embedded memory technology. By following the guidelines outlined in this document, they can ensure the proper implementation and operation of eMMC devices in their products. With the support of JEDEC standards, the industry can continue to advance and thrive in the ever-evolving landscape of solid-state technology.

JEDEC Standard No. 84-B51

-xii-

Table 50 — Block-oriented read commands (class 2) ............................................................................................... 127

Table 51 — Class 3 commands ................................................................................................................................. 127

Table 52 — Block-oriented write commands (class 4).............................................................................................. 128

Table 53 — Block-oriented write protection commands (class 6) ............................................................................ 129

Table 54 — Erase commands (class 5) ...................................................................................................................... 130

Table 55 — I/O mode commands (class 9) ............................................................................................................... 131

Table 56 — Lock Device commands (class 7) .......................................................................................................... 131

Table 57 — Application-specific commands (class 8) .............................................................................................. 131

Table 58 — Security Protocols (class 10) ................................................................................................................. 132

Table 59 — Command Queue (Class 11) .................................................................................................................. 133

Table 60 — Device state transitions .......................................................................................................................... 134

Table 61 — Device state transitions (cont’d) ............................................................................................................ 135

Table 62 — Device state transitions (cont’d) ............................................................................................................ 136

Table 63 — R1 response ........................................................................................................................................... 136

Table 64 — R2 response ........................................................................................................................................... 137

Table 65 — R3 Response .......................................................................................................................................... 137

Table 66 — R4 response ........................................................................................................................................... 137

Table 67 — R5 response ........................................................................................................................................... 137

Table 68 — Device status .......................................................................................................................................... 139

Table 69 — Device Status field/command - cross reference ..................................................................................... 141

Table 70 — Response 1 Status Bit Valid .................................................................................................................. 142

Table 71 — Timing Parameters ................................................................................................................................. 154

Table 72 — Timing Parameters for HS200 and HS400 mode................................................................................... 155

Table 73 — H/W reset timing parameters ................................................................................................................. 159

Table 74 — OCR register definitions ........................................................................................................................ 161

Table 75 — CID Fields ............................................................................................................................................. 162

Table 76 — Device Types ......................................................................................................................................... 162

Table 77 — Valid MDT “y” Field Values ................................................................................................................. 163

Table 78 — CSD Fields ............................................................................................................................................. 164

Table 79 — CSD register structure ........................................................................................................................... 165

Table 80 — System specification version ................................................................................................................. 165

Table 81 — TAAC access-time definition ................................................................................................................ 165

Table 82 — Maximum bus clock frequency definition ............................................................................................. 166

Table 83 — Supported Device command classes ...................................................................................................... 166

Table 84 — Data block length ................................................................................................................................... 166

Table 85 — DSR implementation code table ............................................................................................................ 167

Table 86 — V

(min) current consumption ............................................................................................................. 168

Table 87 — V

(max) current consumption ............................................................................................................ 168

Table 88 — Multiplier factor for device size............................................................................................................. 169

Table 89 — R2W_FACTOR ..................................................................................................................................... 170

Table 90 — File formats ............................................................................................................................................ 171

Table 91 — ECC type ............................................................................................................................................... 171

Table 92 — CSD field command classes .................................................................................................................. 172

Table 93 — Extended CSD ....................................................................................................................................... 173

Table 94 — EXT_SECURITY_ERR byte description .............................................................................................. 178

Table 95 — Device-supported command sets ........................................................................................................... 178

Table 96 — HPI features ........................................................................................................................................... 178

JEDEC Standard No. 84-B51

-xiii-

Table 97 — Background operations support ............................................................................................................. 179

Table 98 — Context Management Context Capabilities ........................................................................................... 180

Table 99 — Extended CSD Register Support............................................................................................................ 180

Table 100 — SUPPORTED_MODES ...................................................................................................................... 180

Table 101 — FFU FEATURES ................................................................................................................................. 180

Table 102 — MODE_OPERATION_CODES timeout definition ............................................................................ 181

Table 103 — Device life time estimation type B value ............................................................................................. 182

Table 104 — Device life time estimation type A value ............................................................................................. 183

Table 105 — Pre EOL info value .............................................................................................................................. 183

Table 106 — Optimal read size value ....................................................................................................................... 184

Table 107 — Optimal write size value ...................................................................................................................... 184

Table 108 — Optimal trim unit size value ................................................................................................................ 184

Table 109 — Generic Switch Timeout Definition ..................................................................................................... 185

Table 110 — Power off long switch timeout definition ............................................................................................ 185

Table 111 — Background operations status .............................................................................................................. 186

Table 112 — Correctly programmed sectors number ................................................................................................ 186

Table 113 — Initialization Time out value ................................................................................................................ 186

Table 114 — Cache Flushing Policy ......................................................................................................................... 187

Table 115 — TRIM/DISCARD Time out value........................................................................................................ 187

Table 116 — SEC Feature Support ........................................................................................................................... 188

Table 117 — Secure Erase time-out value ................................................................................................................ 189

Table 118 — Secure Erase time-out value ................................................................................................................ 189

Table 119 — Boot information .................................................................................................................................. 190

Table 120 — Boot partition size ................................................................................................................................ 190

Table 121 — Access size ........................................................................................................................................... 191

Table 122 — Superpage size ..................................................................................................................................... 191

Table 123 — Erase-unit size ...................................................................................................................................... 191

Table 124 — Erase timeout values ............................................................................................................................ 192

Table 125 — Reliable write sector count .................................................................................................................. 192

Table 126 — Write protect group size ....................................................................................................................... 192

Table 127 — S_C_VCC, S_C_VCCQ Sleep Current ............................................................................................... 193

Table 128 — Production State Awareness timeout definition ................................................................................... 193

Table 129 — Sleep/awake timeout values ................................................................................................................. 194

Table 130 — Sleep Notification timeout values ........................................................................................................ 194

Table 131 — SECURE_WP_INFO ........................................................................................................................... 195

Table 132 — R/W access performance values .......................................................................................................... 196

Table 133 — Power classes ....................................................................................................................................... 197

Table 134 — Partition switch timeout definition ...................................................................................................... 198

Table 135 — Out-of-interrupt timeout definition ...................................................................................................... 198

Table 136 — Supported Driver Strengths ................................................................................................................. 199

Table 137 — Device types ........................................................................................................................................ 200

Table 138 — CSD register structure.......................................................................................................................... 200

Table 139 — Extended CSD revisions ...................................................................................................................... 201

Table 140 — Standard MMC command set revisions ............................................................................................... 201

Table 141 — Power class codes ................................................................................................................................ 201

Table 142 — HS_TIMING (timing and driver strength) ........................................................................................... 202

Table 143 — HS_TIMING Interface values ............................................................................................................. 202

JEDEC Standard No. 84-B51

-xiv-

Table 144 — BUS_WIDTH ...................................................................................................................................... 203

Table 145 — Bus Mode Selection ............................................................................................................................. 203

Table 146 — Erased memory content values ............................................................................................................ 203

Table 147 — Boot configuration bytes ...................................................................................................................... 204

Table 148 — Boot configuration protection .............................................................................................................. 205

Table 149 — Boot bus configuration ........................................................................................................................ 205

Table 150 — Bus Width and Timing Mode Transition ............................................................................................. 206

Table 151 — ERASE_GROUP_DEF ........................................................................................................................ 207

Table 152 — BOOT_WP_STATUS ......................................................................................................................... 207

Table 153 — BOOT area Partitions write protection ................................................................................................ 208

Table 154 — User area write protection .................................................................................................................... 210

Table 155 — FW Update Disable ............................................................................................................................. 211

Table 156 — RPMB Partition Size............................................................................................................................ 211

Table 157 — Write reliability setting ........................................................................................................................ 212

Table 158 — Write reliability parameter register ...................................................................................................... 213

Table 159 — Background operations enable ............................................................................................................. 214

Table 160 — H/W reset function ............................................................................................................................... 215

Table 161 — HPI management ................................................................................................................................. 215

Table 162 — Partitioning Support ............................................................................................................................. 216

Table 163 — Max. Enhanced Area Size .................................................................................................................... 216

Table 164 — Partitions Attribute .............................................................................................................................. 217

Table 165 — Partition Setting ................................................................................................................................... 217

Table 166 — General Purpose Partition Size ............................................................................................................ 218

Table 167 — Enhanced User Data Area Size ............................................................................................................ 219

Table 168 — Enhanced User Data Start Address ...................................................................................................... 219

Table 169 — Secure Bad Block management ........................................................................................................... 219

Table 170 — PRODUCTION_STATE_AWARENESS states ................................................................................. 220

Table 171 — PERIODIC_WAKEUP ........................................................................................................................ 221

Table 172 — CMD26 and CMD27 in DDR mode Support ...................................................................................... 221

Table 173 — Initialization Time out value ................................................................................................................ 222

Table 174 — Class 6 usage ....................................................................................................................................... 222

Table 175 — EXCEPTION_EVENTS_CTRL[56] ................................................................................................... 223

Table 176 — EXCEPTION_EVENTS_CTRL[57] ................................................................................................... 223

Table 177 — EXCEPTION_EVENTS_STATUS[54] .............................................................................................. 223

Table 178 — EXCEPTION_EVENTS_STATUS[55] .............................................................................................. 223

Table 179 — First Byte EXT_PARTITIONS_ATTRIBUTE[52] ............................................................................. 224

Table 180 — Second Byte EXT_PARTITIONS_ATTRIBUTE[53] ........................................................................ 224

Table 181 — CONTEXT_CONF configuration format ............................................................................................ 225

Table 182 — Packed Command Status Register ....................................................................................................... 225

Table 183 — Valid POWER_OFF_NOTIFICATION values ................................................................................... 226

Table 184 — CACHE ENABLE ............................................................................................................................... 226

Table 185 — FLUSH CACHE .................................................................................................................................. 227

Table 186 — BARRIER_CTRL ................................................................................................................................ 227

Table 187 — Valid MODE_CONFIG values ............................................................................................................ 227

Table 188 — Valid MODE_OPERATION_CODES values ..................................................................................... 228

Table 189 — FFU Status codes ................................................................................................................................. 228

Table 190 — Production State Awareness Enablement ............................................................................................ 229

JEDEC Standard No. 84-B51

-xv-

Table 191 — Secure Removal Type .......................................................................................................................... 230

Table 192 — Command Queue Mode Enable ........................................................................................................... 230

Table 193 — SECURE_WP_MODE_ENABLE ....................................................................................................... 231

Table 194 — SECURE _WP_MODE_CONFIG ...................................................................................................... 232

Table 195 — Error correction codes.......................................................................................................................... 233

Table 196 — DSR register content ............................................................................................................................ 242

Table 197 — General operating conditions ............................................................................................................... 244

Table 198 — e•MMC power supply voltage ............................................................................................................. 246

Table 199 — e•MMC voltage combinations ............................................................................................................. 246

Table 200 — Capacitance and Resistors ................................................................................................................... 247

Table 201 — AC Overshoot/Undershoot Specification ............................................................................................ 249

Table 202 — Open-drain bus signal level ................................................................................................................. 250

Table 203 — Push-pull signal level—high-voltage e•MMC ..................................................................................... 250

Table 204 — Push-pull signal level—1.70 V -1.95 V V

CCQ

voltage Range .............................................................. 250

Table 205 — Push-pull signal level—1.1 V-1.3 V V

CCQ

range e•MMC ................................................................... 250

Table 206 — I/O driver strength types ...................................................................................................................... 251

Table 207 — Driver Type-0 AC Characteristics ...................................................................................................... 252

Table 208 — High-speed Device interface timing .................................................................................................... 253

Table 209 — Backward-compatible Device interface timing.................................................................................... 254

Table 210 — High-speed dual rate interface timing .................................................................................................. 256

Table 211 — HS200 Clock signal timing .................................................................................................................. 257

Table 212 — HS200 Device input timing ................................................................................................................. 258

Table 213 — Output timing ....................................................................................................................................... 259

Table 214 — Temperature Conditions ...................................................................................................................... 260

Table 215 — HS400 Device input timing ................................................................................................................. 261

Table 216 — HS400 Device Output timing .............................................................................................................. 262

Table 217 — HS400 Capacitance and Resistors ....................................................................................................... 263

Table 218 — HS400 CMD Response timing ............................................................................................................ 264

Table 219 — e•MMC host requirements for Device classes ..................................................................................... 266

Table 220 — New Features List for device type ....................................................................................................... 267

Table A.221 — Macro commands ............................................................................................................................. 270

Table A.222 — Forward-compatible host interface timing ....................................................................................... 280

Table A.223 — Bus testing for eight data lines ......................................................................................................... 283

Table A.224 — Bus testing for four data lines .......................................................................................................... 283

Table A.225 — Bus testing for one data line............................................................................................................. 283

Table A.226 — XNOR values ................................................................................................................................... 284

Table A.227 — Package Case Temp (Tc) per current consumption ......................................................................... 290

Table B.228 — Handling of Error Conditions in CQE.............................................................................................. 301

Table B.229 — Task Descriptor Structure; Lower 64 bits (Data Transfer tasks) ...................................................... 302

Table B.230 — Task Descriptor Structure; Upper 64 bits ......................................................................................... 302

Table B.231 — Task Descriptor Fields ..................................................................................................................... 303

Table B.232 — Transfer Descriptor Structure (32-bit addressing) ............................................................................ 304

Table B.233 — Transfer Descriptor Structure (64-bit addressing) ............................................................................ 304

Table B.234 — Transfer Descriptor Fields ............................................................................................................... 304

Table B.235 — Task Descriptor Structure: Lower 64 bits (for DCMD tasks) .......................................................... 305

Table B.236 — Task Descriptor Fields (for DCMD tasks) ....................................................................................... 305

Table B.237 — CQE Register Map ........................................................................................................................... 307

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