PN532近距离通信控制器技术手册

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PN532 数据手册 PN532 是一款高度集成的无线收发器模块，用于 13.56MHz 的无线通信，基于 80C51 微控制器核心。它支持六种不同的操作模式：ISO/IEC 14443A/MIFARE 读取器/写入器、FeliCa 读取器/写入器、ISO/IEC 14443B 读取器/写入器、ISO/IEC 14443A/MIFARE 卡模拟模式、FeliCa 卡模拟模式和 ISO/IEC 18092、ECMA340 点对点模式。 PN532 实现了 ISO/IEC 14443A/MIFARE 兼容卡和 transponder 的调制和解码。它可以处理完整的 ISO/IEC 14443A 帧和错误检测（奇偶校验和 CRC）。PN532 还支持 MIFARE Classic 1K 或 MIFARE Classic 4K 卡模拟模式。 PN532 支持使用 MIFARE 高速传输，最高可达 424kbit/s 双向传输速度。它还可以对 FeliCa 编码信号进行调制和解码，处理 FeliCa 帧和错误检测。PN532 还支持使用 FeliCa 高速传输，最高可达 424kbit/s 双向传输速度。 PN532 的主要特点包括： * 高度集成的设计，集成了调制器、解码器和微控制器核心于一体 * 支持六种不同的操作模式，满足不同的应用需求 * 高速传输速度，最高可达 424kbit/s 双向传输速度 * 支持 MIFARE 和 FeliCa 两种不同的卡类型 * 具有高可靠性和高安全性 PN532 广泛应用于近场通信（NFC）、物联网（IoT）、智能家居、智能支付、身份识别等领域。在 NFC 应用中，PN532 可以作为读取器或写入器，用于读取或写入 NFC 标签或卡。它还可以用于实现点对点的数据传输，例如在智能手机或平板电脑之间的数据传输。在 IoT 应用中，PN532 可以作为数据采集器或数据传输器，用于收集和传输感知数据或控制命令。它还可以用于实现智能家居系统中的智能控制和自动化。在身份识别应用中，PN532 可以作为身份识别器，用于识别和验证个人身份信息。它还可以用于实现智能支付系统中的身份验证和交易处理。 PN532 是一款功能强大且高度集成的无线收发器模块，广泛应用于 NFC、IoT、智能家居、智能支付、身份识别等领域。

Product data sheet

COMPANY PUBLIC

Rev. 3.6 — 28 November 2017

115436 16 of 222

NXP Semiconductors

PN532/C1

Near Field Communication (NFC) controller

8.1.4 PCON module

The Power Control (PCON) module is configured using the PCON SFR register.

8.1.5 Interrupt Controller

The interrupt controller has the following features:

• 13 interrupt sources

• Interrupt enable registers IE0 and IE1

• Interrupt priority registers IP0 and IP1

• Wake-up from Power-Down state

8.1.5.1 Interrupt vectors

The mapping between interrupt sources and interrupt vectors is shown in Table 9

Table 7. PCON register (SFR: address 87h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol SMOD - CPU_PD -

Reset 0 00000 0 0

Access R/WRRRRRR/WR/W

Table 8. Description of PCON bits

Bit Symbol Description

7SMODSerial MODe:

When set to logic 1, the baud rate of the Debug UART is doubled

6 to 3 - Reserved.

1CPU_PDPower-down:

When set to logic 1, the microcontroller goes in Power-down mode

0 Reserved This bit should only ever contain logic 0.

Table 9. Interrupt vector

Interrupt

number

Interrupt

vector

Interrupt sources Incremental priority level

(conflict resolution level)

0 0003h External P32_INT0 Highest

1 000Bh Timer0 interrupt

2 0013h External P33_INT1

3 001Bh Timer1 interrupt

4 0023h Debug UART interrupt

5 002Bh Timer2 interrupt

6 0033h NFC-WI interrupt

7 003Bh LDO overcurrent interrupt

8 0043h Reserved

9 004Bh CIU interrupt 1

10 0053h CIU interrupt 0

11 005Bh I

C interrupt

12 0063h SPI, FIFO, or HSU interrupts

13 006Bh Reserved

14 0073h General Purpose IRQ Lowest

Product data sheet

COMPANY PUBLIC

Rev. 3.6 — 28 November 2017

115436 18 of 222

NXP Semiconductors

PN532/C1

Near Field Communication (NFC) controller

The 2 following tables describe IE1.

8.1.5.3 Interrupt prioritization: IP0 and IP1 registers

Each interrupt source can be individually programmed to be one of two priority levels by

setting or clearing a bit in the interrupt priority registers IP0 and IP1. If two interrupt

requests of different priority levels are received simultaneously, the request with the high

priority is serviced first. On the other hand, if the interrupts are of the same priority,

precedence is resolved by comparing their respective conflict resolution levels (see

Table 9 on page 16

for details). The processing of a low priority interrupt can be

interrupted by one with a high priority.

A RETI (Return From Interrupt) instruction jumps to the address immediately succeeding

the point at which the interrupt was serviced. The instruction found at the return address

will be executed, prior to servicing any pending interrupts.

Table 12. Interrupt controller IE1 register (SFR: address E8h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol IE1_7 - IE1_5 IE1_4 IE1_3 IE1_2 - IE1_0

Reset 0 0 000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 13. Description of IE1 bits

Bit Symbol Description

7 IE1_7 General purpose IRQ interrupt enable.

When set to logic 1, enables interrupt function of P34, P35, P50_SCL and P71

according to their respective enable and level control bits. See Table 19 on

page 20, Table 137 on page 95 and Table 143 on page 97.

6 - Reserved. This bit must be set to logic 0

5 IE1_5 FIFO, SPI and HSU interrupt enable.

When set to logic 1, enables FIFO interrupts, SPI interrupts, HSU interrupt.

In HSU mode, the interrupt is when NSS is at logic 0.

For the FIFO interrupts, see Table 112 on page 76

For the SPI interrupts, see Table 122 on page 81.

4 IE1_4 I2C interrupt enable.

When set to logic 1, enables I

C interrupt. See Table 77 on page 54.

3 IE1_3 CIU interrupt 0 enable.

When set to logic 1, enables CIU interrupt 0: CIU_IRQ_0. See Table 190 on

page 151.

2 IE1_2 CIU interrupt 1 enable.

When set to logic 1, enables the CIU interrupt 1: CIU_IRQ_1. See Table 190

on page 151.

1 - Reserved. This bit must be set to logic 0.

0 IE1_0 LDO overcurrent interrupt enable.

When set to logic 1, enables the LDO overcurrent detection interrupt. See

Table 127 on page 88

Product data sheet

COMPANY PUBLIC

Rev. 3.6 — 28 November 2017

115436 20 of 222

NXP Semiconductors

PN532/C1

Near Field Communication (NFC) controller

8.1.5.4 General purpose IRQ control

The general purpose interrupts are controlled by register GPIRQ.

NOTE: this is not a standard feature of the 8051.

[1] The bit IE1_7 of register IE1 (see Table 13 on page 18) has also to be set to logic 1 to enable the

corresponding CPU interrupt.

Table 18. GPIRQ register (address 6107h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol gpirq_

level_

P71

gpirq_

level_

P50

gpirq_

level_

P35

gpirq_

level_

P34

gpirq_

enable

_P71

gpirq_

enable_

P50

gpirq_

enable_

P35

gpirq_

enable_

P34

Reset 00000000

Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 19. Description of GPIRQ bits

Bit Symbol Description

7 gpirq_level_P71 Configures the polarity of signal on P71 to generate a GPIRQ

interrupt event (assuming gpirq_enable_P71 is set).

When set to logic 0, an interrupt will be generated if P71 is at logic 0.

When set to logic 1, an interrupt will be generated if P71 is at logic 1.

6 gpirq_level_P50 Configures the polarity of signal on P50 to generate a GPIRQ

interrupt event (assuming gpirq_enable_P50 is set).

When set to logic 0, an interrupt will be generated if P50_SCL is at logic 0.

When set to logic 1, an interrupt will be generated if P50_SCL is at logic 1.

5 gpirq_level_P35 Configures the polarity of signal on P35 to generate a GPIRQ

interrupt event (assuming gpirq_enable_P35 is set).

When set to logic 0, an interrupt will be generated if P35 is at logic 0.

When set to logic 1, an interrupt will be generated if P35 is at logic 1.

4 gpirq_level_P34 Configures the polarity of signal on P34 to generate a GPIRQ

interrupt event (assuming gpirq_enable_P34 is set).

When set to logic 0, an interrupt will be generated if P34 is at logic 0.

When set to logic 1, an interrupt will be generated if P34 is at logic 1.

Remark: If hide_svdd_sig of the register control_rngpower is set and

gpirq_enable_P34 is also set then this bit will be asserted independently

of the level on the pad P34.

3 gpirq_enable_P71 When set to logic 1, enables pad P71 to generate a GPIRQ interrupt

event.

[1]

2 gpirq_enable_P50 When set to logic 1, enables pad P50_SCL to generate a GPIRQ interrupt

event.

[1]

1 gpirq_enable_P35 When set to logic 1, enables pad P35 to generate a GPIRQ interrupt

event.

[1]

0 gpirq_enable_P34 When set to logic 1, enables pad P34 to generate a GPIRQ interrupt

event.

[1]

剩余221页未读，继续阅读

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