NXP i.MX6 UltraLite 数据手册：高性能低功耗处理器

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"IMX6UL数据手册.pdf 是NXP Semiconductors发布的一份技术文档，涵盖了MCIMX6UL系列处理器的详细技术规格。这份手册的版本为2.2，发布日期为2017年5月。文档中提到了多个型号的处理器，如MCIMX6G1CVM05AA、MCIMX6G2CVM05AB等，这些都属于i.MX6 UltraLite家族。处理器采用不同封装形式，包括14x14mm和9x9mm的BGA封装，引脚间距分别为0.8mm和0.5mm。订购信息可在第3页的表1中找到。" i.MX6 UltraLite是NXP公司推出的一款高性能、超低功耗的处理器系列，它基于先进的单核ARM Cortex-A7架构，运行频率最高可达528MHz。该处理器的一大特点是内置了电源管理模块，这降低了外部电源供应的复杂性，简化了电源序列设计。在内存接口方面，i.MX6 UltraLite支持LPDDR2、DDR3、DDR3L、裸片及管理式NAND闪存、NOR闪存、eMMC以及四线SPI等多种类型，为连接各种外围设备提供了便利，如WLAN、蓝牙、GPS、显示屏和摄像头传感器。此外，i.MX6 UltraLite处理器特别适用于需要高效能、低功耗处理能力的应用场景。其广泛的应用领域可能包括嵌入式系统、物联网(IoT)设备、工业控制、智能家居、车载信息娱乐系统等。由于其强大的集成性和灵活性，开发者可以利用这款处理器构建出性能卓越且能耗较低的解决方案。处理器特性： 1. 单核ARM Cortex-A7核心：提供高性能计算能力，同时保持低功耗。 2. 内置电源管理模块：简化电源设计，优化系统能耗。 3. 多样化的内存接口：适应不同的存储需求和应用环境。 4. 完善的外设接口：支持多种通信协议，便于连接各种外部硬件。 5. 不同封装选项：满足不同产品尺寸和成本的要求。 i.MX6 UltraLite处理器通过其高效的处理器核心、全面的内存支持和丰富的接口选择，成为开发低功耗、高性能应用的理想平台，尤其适合那些对体积、功耗和成本有严格要求的项目。设计者可以根据具体应用需求，结合手册中的详细信息来选择合适的型号和配置，实现最佳的系统设计方案。

i.MX 6UltraLite Applications Processors for Industrial Products, Rev. 2.2, 05/2017

16 NXP Semiconductors

Modules list

uSDHC1

uSDHC2

SD/MMC and SDXC

Enhanced Multi-Media

Card / Secure Digital Host

Controller

Connectivity

Peripherals

i.MX 6UltraLite specific SoC characteristics:

All four MMC/SD/SDIO controller IPs are identical and

are based on the uSDHC IP. They are:

• Fully compliant with MMC command/response sets

and Physical Layer as defined in the Multimedia

Card System Specification, v4.5/4.2/4.3/4.4/4.41/

including high-capacity (size > 2 GB) cards HC

MMC.

• Fully compliant with SD command/response sets

and Physical Layer as defined in the SD Memory

Card Specifications, v3.0 including high-capacity

SDXC cards up to 2 TB.

• Fully compliant with SDIO command/response sets

and interrupt/read-wait mode as defined in the SDIO

Card Specification, Part E1, v3.0

Two ports support:

• 1-bit or 4-bit transfer mode specifications for SD and

SDIO cards up to UHS-I SDR104 mode (104 MB/s

max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for

MMC cards up to 52 MHz in both SDR and DDR

modes (104 MB/s max)

• 4-bit or 8-bit transfer mode specifications for eMMC

chips up to 200 MHz in HS200 mode (200 MB/s max)

USB Universal Serial Bus 2.0 Connectivity

Peripherals

USBO2 (USB OTG1 and USB OTG2) contains:

• Two high-speed OTG 2.0 modules with integrated

HS USB PHYs

• Support eight Transmit (TX) and eight Receive (Rx)

endpoints, including endpoint 0

WDOG1

WDOG3

Watch Dog Timer Peripherals The Watch Dog Timer supports two comparison points

during each counting period. Each of the comparison

points is configurable to evoke an interrupt to the ARM

core, and a second point evokes an external event on

the WDOG line.

WDOG2

(TZ)

Watch Dog (TrustZone) Timer Peripherals The TrustZone Watchdog (TZ WDOG) timer module

protects against TrustZone starvation by providing a

method of escaping normal mode and forcing a switch

to the TZ mode. TZ starvation is a situation where the

normal OS prevents switching to the TZ mode. Such

situation is undesirable as it can compromise the

system’s security. Once the TZ WDOG module is

activated, it must be serviced by TZ software on a

periodic basis. If servicing does not take place, the timer

times out. Upon a time-out, the TZ WDOG asserts a TZ

mapped interrupt that forces switching to the TZ mode.

If it is still not served, the TZ WDOG asserts a security

violation signal to the CSU. The TZ WDOG module

cannot be programmed or deactivated by a normal

mode SW.

Table 3. i.MX 6UltraLite Modules List (continued)

Block Mnemonic Block Name Subsystem Brief Description

Modules list

i.MX 6UltraLite Applications Processors for Industrial Products, Rev. 2.2, 05/2017

NXP Semiconductors 17

3.1 Special signal considerations

Table 4 lists special signal considerations for the i.MX 6UltraLite processors. The signal names are listed

in alphabetical order.

The package contact assignments can be found in Section 6, “Package information and contact

assignments".” Signal descriptions are provided in the i.MX 6UltraLite Reference Manual

(IMX6ULRM).

Table 4. Special Signal Considerations

Signal Name Remarks

CCM_CLK1_P/

CCM_CLK1_N

One general purpose differential high speed clock Input/output is provided.

It can be used:

• To feed external reference clock to the PLLs and further to the modules inside SoC.

• To output internal SoC clock to be used outside the SoC as either reference clock or as a

functional clock for peripherals.

See the i.MX 6UltraLite Reference Manual (IMX6ULRM) for details on the respective clock trees.

Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding

CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.

Termination should be provided in case of high frequency signals.

After initialization, the CLK1 input/output can be disabled (if not used). If unused either or both of

the CLK1_N/P pairs may remain unconnected.

RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz

crystal, (100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.

Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal

load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to

account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but

relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO

to either power or ground (>100 M). This will debias the amplifier and cause a reduction of startup

margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.

If it is desired to feed an external low frequency clock into RTC_XTALI, the RTC_XTALO pin must

remain unconnected or driven with a complimentary signal. The logic level of this forcing clock

should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical

conditions.

In case when high accuracy real time clock are not required system may use internal low frequency

ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO

unconnected.

XTALI/XTALO A 24.0 MHz crystal should be connected between XTALI and XTALO.

The crystal must be rated for a maximum drive level of 250 W. An ESR (equivalent series

resistance) of typical 80  is recommended. NXP BSP (board support package) software requires

24 MHz on XTALI/XTALO.

The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this

case, XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pF

capacitor. Please refer to the EVK board reference design for details. The logic level of this forcing

clock cannot exceed NVCC_PLL level.

If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter

requirements. See OSC24M chapter and relevant interface specifications chapters for details.

i.MX 6UltraLite Applications Processors for Industrial Products, Rev. 2.2, 05/2017

18 NXP Semiconductors

Modules list

DRAM_VREF When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the

NVCC_DRAM supply. The user can tie DDR_VREF to a precision external resistor divider. Use a

1k 0.5% resistor to GND and a 1 k 0.5% resistor to NVCC_DRAM. Shunt each resistor with a

closely-mounted 0.1 µF capacitor.

To reduce supply current, a pair of 1.5 k 0.1% resistors can be used. Using resistors with

recommended tolerances ensures the ± 2% DDR_VREF tolerance (per the DDR3 specification) is

maintained when two DDR3 ICs plus the i.MX 6UltraLite are drawing current on the resistor divider.

ZQPAD DRAM calibration resistor 240  1% used as reference during DRAM output buffer driver

calibration should be connected between this pad and GND.

GPANAIO This signal is reserved for NXP manufacturing use only. This output must remain unconnected.

JTAG_nnnn The JTAG interface is summarized in Table 5. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the non-connected condition is eliminated

if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

should be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX 6UltraLite reference manual. Both names refer

to the same signal. JTAG_MOD must be externally connected to GND for normal operation.

Termination to GND through an external pull-down resistor (such as 1 k) is allowed. JTAG_MOD

set to hi configures the JTAG interface to mode compliant with IEEE1149.1 standard. JTAG_MOD

set to low configures the JTAG interface for common SW debug adding all the system TAPs to the

chain.

NC These signals are No Connect (NC) and should be floated by the user.

POR_B This cold reset negative logic input resets all modules and logic in the IC.

May be used in addition to internally generated power on reset signal (logical AND, both internal

and external signals are considered active low).

ONOFF ONOFF can be configured in debounce, off to on time, and max time-out configurations. The

debounce and off to on time configurations supports 0, 50, 100 and 500 ms. Debounce is used to

generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than the

debounce time, the power off interrupt is generated. Off to on time supports the time it takes to

request power on after a configured button press time has been reached. While in the OFF state,

if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON.

Max time-out configuration supports 5, 10, 15 seconds and disable. Max time-out configuration

supports the time it takes to request power down after ONOFF button has been pressed for the

defined time.

TEST_MODE TEST_MODE is for NXP factory use. The user must tie this pin directly to GND.

Table 5. JTAG Controller Interface Summary

JTAG I/O Type On-chip Termination

JTAG_TCK Input 47 kpull-up

JTAG_TMS Input 47 kpull-up

JTAG_TDI Input 47 kpull-up

JTAG_TDO 3-state output Keeper

Table 4. Special Signal Considerations (continued)

Signal Name Remarks

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