DDR4 SDRAM技术规格：1.2V低功耗，高密度内存模块

需积分: 5 143 浏览量更新于2024-07-08 1 收藏 11.14MB PDF 举报

"4GB DDR4 SDRAM 数据表，详细介绍了DDR4 x16内存模块，包括其特性、规格和功能。" DDR4 SDRAM（Double Data Rate第四代同步动态随机存取存储器）是一种高性能的内存技术，广泛应用于现代计算机和其他电子设备中。以下是对该DDR4 SDRAM芯片主要特性和功能的详细解释： 1. **电压规格**：DDR4内存的工作电压显著降低，VDD和VDDQ均设定在1.2V±60mV，相比DDR3的1.5V或1.35V更节能。VPP为2.5V，允许有一定的电压浮动。 2. **内部参考电压生成**：芯片内集成了可调整的VREFDQ，能精确控制数据线的参考电压，确保信号质量。 3. **I/O特性**：使用1.2V的伪开漏（Pseudo Open-Drain）I/O，这种设计降低了功耗，同时提高了信号的完整性。 4. **工作温度和刷新**：在0°C至95°C的温度范围内，内存需要64ms进行8192周期的刷新；在85°C至95°C时，刷新周期缩短到32ms，以应对高温环境。 5. **内存架构**：具有8个内部银行，分为2组每组4个，这样的设计提高了内存的并发访问能力。 6. **8n位预取架构**：预取是指在实际读写操作之前先获取数据，8n位预取意味着每次读写操作可以处理8倍于数据线宽度的数据，提高数据传输效率。 7. **可编程数据 strobe 前导**：允许用户根据系统需求调整数据 strobe 的预前导，优化信号同步。 8. **命令/地址延迟(CAL)**：允许微调命令和地址信号的延迟，确保与系统的精确同步。 9. **多用途寄存器**：提供了读写功能，可以读取和写入寄存器中的信息，增强内存的灵活性。 10. **写入和读取校准**：确保数据在传输过程中的准确性和一致性。 11. **自刷新模式**：当系统处于低功耗状态时，内存进入自刷新模式，减少电力消耗。 12. **低功耗自动自刷新(LPASR)**：进一步降低了自刷新状态下的功率消耗。 13. **温度控制刷新(TCR)**：根据芯片温度动态调整刷新策略，确保数据的稳定性。 14. **细粒度刷新**：允许更精细的刷新控制，提高内存的可靠性。 15. **自刷新中止**：在需要时可中断自刷新过程，以便系统能快速恢复到正常操作。 16. **最大功率节省**：整个设计的目标是尽可能减少功率消耗，提升能效。 17. **输出驱动器校准**：自动校准输出驱动器，确保信号质量。 18. **开/关阻抗确定(ODT)**：支持静态和动态的开/关阻抗设定，优化信号完整性和减少信号干扰。 19. **数据总线反转(DBI)**：用于数据总线的错误检测，通过反转数据线来检测并修正错误。 20. **命令/地址(CA)奇偶校验**：增加了额外的错误检测机制，提高数据传输的可靠性。 21. **数据总线写循环冗余检查(CRC)**：提供数据完整性检查，防止数据传输过程中的错误。 22. **按DRAM地址寻址**：每个DRAM芯片都有独立的地址，便于管理和故障排查。 23. **连接性测试**：确保内存模块与主板的正确连接，通过自检保证兼容性和稳定性。 24. **符合JEDEC标准**：此DDR4 SDRAM芯片遵循JEDEC JESD-79-4标准，确保了与其他兼容硬件的互操作性。此外，文件还提到了不同的选项，如不同版本（标记为A）、封装尺寸（96球FBGA，7.5mmx13.5mm），以及不同的时序选项，如0.625ns@CL=24（DDR4-3200）、0.750ns@CL=19（DDR4-2666）和0.833ns@CL=16（DDR4-2400），这些表示不同的时钟周期和CAS延迟，对应不同速度等级的DDR4内存。

Table 103: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200 ................ 274

Table 104: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c ............. 275

Table 105: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c ............. 275

Table 106: Cross Point Voltage For Differential Input Signals DQS ................................................................... 277

Table 107: DQS Differential Input Slew Rate Definition .................................................................................. 278

Table 108: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 278

Table 109: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 279

Table 110: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications ...................................................... 280

Table 111: CK Overshoot and Undershoot/ Specifications .............................................................................. 280

Table 112: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications ................................................ 281

Table 113: Single-Ended Output Levels ......................................................................................................... 282

Table 114: Single-Ended Output Slew Rate Definition .................................................................................... 282

Table 115: Single-Ended Output Slew Rate .................................................................................................... 283

Table 116: Differential Output Levels ............................................................................................................. 283

Table 117: Differential Output Slew Rate Definition ....................................................................................... 284

Table 118: Differential Output Slew Rate ....................................................................................................... 285

Table 119: Connectivity Test Mode Output Levels .......................................................................................... 285

Table 120: Connectivity Test Mode Output Slew Rate ..................................................................................... 287

Table 121: Output Driver Electrical Characteristics During Connectivity Test Mode ......................................... 288

Table 122: Strong Mode (34ȍ) Output Driver Electrical Characteristics ........................................................... 289

Table 123: Weak Mode (48ȍ) Output Driver Electrical Characteristics ............................................................. 290

Table 124: Output Driver Sensitivity Definitions ............................................................................................ 291

Table 125: Output Driver Voltage and Temperature Sensitivity ....................................................................... 291

Table 126: Alert Driver Voltage ...................................................................................................................... 292

Table 127: ODT DC Characteristics ............................................................................................................... 293

Table 128: ODT Sensitivity Definitions .......................................................................................................... 294

Table 129: ODT Voltage and Temperature Sensitivity ..................................................................................... 295

Table 130: ODT Timing Definitions ............................................................................................................... 295

Table 131: Reference Settings for ODT Timing Measurements ........................................................................ 296

Table 132: DRAM Package Electrical Specifications for x4 and x8 Devices ....................................................... 298

Table 133: DRAM Package Electrical Specifications for x16 Devices ................................................................ 299

Table 134: Pad Input/Output Capacitance ..................................................................................................... 301

Table 135: Thermal Characteristics ............................................................................................................... 302

Table 136: Basic I

, I

, and I

DDQ

Measurement Conditions .......................................................................... 304

Table 137: I

DD0

and I

PP0

Measurement-Loop Pattern

.................................................................................... 308

Table 138: I

DD1

Measurement – Loop Pattern

............................................................................................... 309

Table 139: I

DD2N

, I

DD3N

, and I

PP3P

Measurement – Loop Pattern

.................................................................... 310

Table 140: I

DD2NT

and I

DDQ2NT

Measurement – Loop Pattern

......................................................................... 311

Table 141: I

DD4R

Measurement – Loop Pattern

.............................................................................................. 312

Table 142: I

DD4W

Measurement – Loop Pattern

............................................................................................. 313

Table 143: I

DD4Wc

Measurement – Loop Pattern

............................................................................................ 314

Table 144: I

DD5R

Measurement – Loop Pattern

.............................................................................................. 315

Table 145: I

DD7

Measurement – Loop Pattern

............................................................................................... 316

Table 146: Timings used for I

, I

, and I

DDQ

Measurement – Loop Patterns .................................................. 317

Table 147: I

, I

, and I

DDQ

Current Limits ................................................................................................... 318

Table 148: DDR4-1600 Speed Bins and Operating Conditions ......................................................................... 320

Table 149: DDR4-1866 Speed Bins and Operating Conditions ......................................................................... 321

Table 150: DDR4-2133 Speed Bins and Operating Conditions ......................................................................... 322

Table 151: DDR4-2400 Speed Bins and Operating Conditions ......................................................................... 323

Table 152: DDR4-2666 Speed Bins and Operating Conditions ......................................................................... 325

Table 153: DDR4-3200 Speed Bins and Operating Conditions ......................................................................... 327

Table 154: Refresh Parameters by Device Density ........................................................................................... 328

4Gb: x16 DDR4 SDRAM

Features

PDF: 09005aef85f537bf

4gb_ddr4_dram_2e0d.pdf - Rev. E 7/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

General Notes and Description

Description

The DDR4 SDRAM is a high-speed dynamic random-access memory internally config-

ured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the

x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to ach-

ieve high-speed operation. The 8n-prefetch architecture is combined with an interface

designed to transfer two data words per clock cycle at the I/O pins.

A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit

wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit

wide, one-half-clock-cycle data transfers at the I/O pins.

Industrial Temperature

An industrial temperature (IT) device option requires that the case temperature not ex-

ceed below –40°C or above 95°C. JEDEC specifications require the refresh rate to double

when T

exceeds 85°C; this also requires use of the high-temperature self refresh option.

Additionally, ODT resistance and the input/output impedance must be derated when

operating outside of the commercial temperature range, when T

is between –40°C and

0°C.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL enable mode of operation (normal operation), unless specifically stated other-

wise.

• Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ

term is to be interpreted as any and all DQ collectively, unless specifically stated oth-

erwise.

• The terms "_t" and "_c" are used to represent the true and complement of a differen-

tial signal pair. These terms replace the previously used notation of "#" and/or over-

bar characters. For example, differential data strobe pair DQS, DQS# is now referred

to as DQS_t, DQS_c.

• The term "_n" is used to represent a signal that is active LOW and replaces the previ-

ously used "#" and/or overbar characters. For example: CS# is now referred to as

CS_n.

• The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as

DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise.

• Complete functionality may be described throughout the entire document; any page

or diagram may have been simplified to convey a topic and may not be inclusive of all

requirements.

• Any specific requirement takes precedence over a general statement.

• Any functionality not specifically stated here within is considered undefined, illegal,

and not supported, and can result in unknown operation.

• Addressing is denoted as BG[n] for bank group, BA[n] for bank address, and A[n] for

row/col address.

• The NOP command is not allowed, except when exiting maximum power savings

mode or when entering gear-down mode, and only a DES command should be used.

4Gb: x16 DDR4 SDRAM

General Notes and Description

PDF: 09005aef85f537bf

4gb_ddr4_dram_2e0d.pdf - Rev. E 7/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

• Not all features described within this document may be available on the Rev. A (first)

version.

• Not all specifications listed are finalized industry standards; best conservative esti-

mates have been provided when an industry standard has not been finalized.

• Although it is implied throughout the specification, the DRAM must be used after V

has reached the stable power-on level, which is achieved by toggling CKE at least once

every 8192 ×

REFI. However, in the event CKE is fixed HIGH, toggling CS_n at least

once every 8192 ×

REFI is an acceptable alternative. Placing the DRAM into self re-

fresh mode also alleviates the need to toggle CKE.

• Not all features designated in the data sheet may be supported by earlier die revisions

due to late definition by JEDEC.

Definitions of the Device-Pin Signal Level

• HIGH: A device pin is driving the logic 1 state.

• LOW: A device pin is driving the logic 0 state.

• High-Z: A device pin is tri-state.

• ODT: A device pin terminates with the ODT setting, which could be terminating or tri-

state depending on the mode register setting.

Definitions of the Bus Signal Level

• HIGH: One device on the bus is HIGH, and all other devices on the bus are either ODT

or High-Z. The voltage level on the bus is nominally V

DDQ

• LOW: One device on the bus is LOW, and all other devices on the bus are either ODT

or High-Z. The voltage level on the bus is nominally V

OL(DC)

if ODT was enabled, or

SSQ

if High-Z.

• High-Z: All devices on the bus are High-Z. The voltage level on the bus is undefined as

the bus is floating.

• ODT: At least one device on the bus is ODT, and all others are High-Z. The voltage lev-

el on the bus is nominally V

DDQ

• The specification requires 8,192 refresh commands within 64ms between 0

C and 85

C. This allows for a

REFI of 7.8125μs (the use of "7.8μs" is truncated from 7.8125μs).

The specification also requires 8,192 refresh commands within 32ms between 85

and 95

C. This allows for a

REFI of 3.90625μs (the use of "3.9μs" is truncated from

3.90625μs).

4Gb: x16 DDR4 SDRAM

General Notes and Description

PDF: 09005aef85f537bf

4gb_ddr4_dram_2e0d.pdf - Rev. E 7/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

剩余358页未读，继续阅读

p65432

粉丝: 0
资源: 2

DDR4 SDRAM技术规格：1.2V低功耗，高密度内存模块

4Gb_DDR4_SDRAM.rar

16Gb_32Gb_x4_x8_3DS_DDR4_SDRAM_ddr_ddr4_

三星_DDR2_RAM_命名规则.pdf

DDR4_Product_guide_May.18.pdf

DDR3_Product_guide_Oct.16[2]-0.pdf

DDR4_JESD79-4B.pdf

ddr3_code-0.pdf

Samsung DDR3 Datasheet.pdf.pdf

MODULE4.20.27.E Annex E, R-C E, in 288-Pin, 1.2 V (VDD), PC4-1600-PC4-1866-PC4-2133-PC4-2400-PC4-2666-PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification - 完整英文电子版（31页）.pdf

K4B4G1646D-BC-I_Rev103-0.pdf

最新资源