误差建模在电子测试前沿的应用

需积分: 10 54 浏览量更新于2024-07-25 收藏 13.84MB PDF 举报

《误差建模验证》是电子测试领域的重要课题，它在现代信息技术中扮演着至关重要的角色。本书系列"Verification by Error Modeling"（错误模型验证）由Vishwani D. Agrawal担任咨询编辑，专注于探讨通过模拟和分析潜在错误来确保系统正确性的方法论。该系列汇集了多本专著，每本书都针对特定技术领域进行了深入研究。例如，K.Radecka和Zilic合著的书探讨了错误模型在系统验证中的基础原理和应用，遵循IEEE Std.1450的原则，这是电子产品设计和验证过程中的关键标准。该标准旨在提供一套系统的方法来识别和预防设计阶段的错误，以提升系统的可靠性。 A.Benso和P.Prinetto的著作聚焦于嵌入式系统的故障注入技术和工具，这对于评估硬件的可靠性至关重要。他们的研究帮助设计师理解如何在设计阶段引入故障，以便在实际运行环境中检测和修复潜在问题。 R.Dean Adams的书《High Performance Memory Memory Testing》重点关注高性能内存的测试方法，确保数据存储和处理的准确性。对于现代数据中心和高性能计算设备来说，高效、准确的内存测试是性能的关键保障。 K.Chakrabarty的《SOC (System-on-a-Chip) Testing for Plug-and-Play Test Automation》则关注系统级芯片的自动化测试，这种测试策略对于大规模集成电路的集成和互操作性至关重要，尤其在需要无缝连接的嵌入式系统中。《Test Resource Partitioning for System-on-a-Chip》深入研究了SoC中测试资源的有效分配，优化测试效率和减少测试时间，这对于提高整体系统效能是必不可少的。 C.Stroud的《A Designer's Guide to Built-in Self-Test》为设计者提供了关于内置自测(BIST)的实用指南，这种自我诊断机制能实时检查和报告硬件故障，提高系统的健壮性和维护性。 J.deSousa和P.Cheung合著的《Boundary-Scan Interconnect Diagnosis》专门探讨边界扫描技术在连接诊断中的应用，这是一种无损测试技术，用于检测电路板上复杂互连网络的问题。此外，M.L.Bushnell和V.D.Agrawal合著的书籍涵盖了数字、内存和混合信号VLSI电路的基本电子测试原则，而A.Osseiran的作品则详细解读了IEEE 1149.4标准，这是针对模拟和混合信号电路的边界扫描测试的国际标准。总体而言，"Verification by Error Modeling"系列书籍涵盖了从基础原理到实际应用的广泛内容，对于从事电子设计、验证和测试工作的专业人士来说，是一套不可或缺的参考资料。这些书籍强调了在快速发展的IT行业中，对错误模型进行有效的验证和测试策略的重要性，以确保产品的高质量和可靠性。

Introduction

Specifications are often prepared by a team led by product managers. The

ways in which design tasks are divided and carried out depend on company

practices, resources and the experience of a design team. General trends,

however, are to start with the behavioral modeling. For that purpose, initial

algorithms are represented in hardware description languages (HDLs) like

VHDL or Verilog, or even in higher abstraction languages, like SystemC.

The correctness at this stage is checked by the comparison to the

specification.

After the behavioral model has been verified, the design is partitioned

into smaller, more refined blocks. Whenever possible, these blocks are

represented by intellectual property (IP) cores, while remaining elements are

modeled using structural HDL or schematic capture, Figure 1. Once the

design functionality and estimated performance is satisfactory, the circuit is

synthesized. During the synthesis process, various automated minimization

steps take place. Sometimes, it is necessary to perform manual

modifications, mainly to introduce design-for-test features, including scan,

boundary scan, test point insertion and built-in self-test (BIST). This stage

of a design flow is illustrated by the central part of Figure 1. Finally, after

satisfying timing, area, power and other criteria, a layout is prepared for

fabrication, the rightmost part of Figure 1.

Introduction

the overall time, space and power requirements. A verification plan starts by

identifying all blocks to be verified and by prioritizing verification tasks.

There are no golden rules on how to achieve this partition. Often, critical

are: design structure, confidence of an engineer in his/her abilities, as well as

the inter-company requirements for final products.

The next step is to identify how and what should be verified in the sub-

blocks. It is often not feasible to fully verify all blocks; therefore, some

compromises must be made. Certain elements are must-have features - they

must be correct for the normal functionality of a system, while others are

should-have features, which are only enhancements. Once the priority is

established, the final step is to determine when and how a given sub-block

will be verified. At this point, it must be clear which parts should be verified

through simulation-based methods, how many testbenches are required, and

which elements will be approached through formal methods.

Checking the correctness is the most difficult aspect of the design

process. In practice, verification of any substantial circuit is almost never

completed, as it can never be stated with a certainty that the given circuit is

fully correct - we can only show the presence of an error rather than its

absence.

Little tolerance for hardware errors imposes strict quality standards. For

example, in the aerospace industry it is a common practice to duplicate the

verification effort by assigning more than one engineer to the same task.

This duplication increases chances of catching an error as early as possible.

Since errors found late in a design process can be potentially very costly,

early detection is obviously critical.

The impact of verification on a design process

should be even larger than

that of testing for manufacturing faults. In the latter case, most circuits are

built in compliance with design for testability (DFT) rules. DFT provides

guidance for inserting of testing features such as: Built-in Self Test (BIST)

for embedded memories and datapath elements, scan and boundary scan, test

point insertion [24] and many others. Most of the above practices have been

standardized.

The analogous solution would be to elaborate a set of rules for design for

verification. As of now, however, no such standards exist in spite of the

concerted efforts [16]. Were design process coordinated with verification,

many changes aimed to ease the verification could be incorporated in the

design flow. For example, typical modifications that prove to be very helpful

VERIFICATION – APPROACHES AND

PROBLEMS

Introduction

include inserting additional registers to control, observe and debug internal

signals. Another commonly used approach partitions a design by placing

multiplexers around each block to isolate it from the rest of a circuit during

verification. Finally, employing as many IP cores as possible further

simplifies design and verification process.

Due to the abundance of classes of errors, diverse approaches are used to

verify their presence/absence. Simulations are still the most common way of

design validation; however, with the growing circuit complexity, in many

cases simulations alone might not able to stand up to the task. Formal

methods for design verification are gaining popularity, and are often

recognized as the verification, leaving simulations as a method of validation.

However, in our terminology we do not distinguish among simulations,

semi-formal and formal methods, and refer to all of them as verification.

Simulation of a circuit under a suitable input stimulus, often referred to

as test vectors or testbenches, is the oldest and still the most extensively used

in practice verification method [17], [18]. Simulations are applied to verify

circuits at various stages of a design process.

This approach is related to another important topic in circuit design, that

of testing for manufacturing faults. We argue that common to the use of

simulations in testing and verification are: error models, test vector

generation and, sometimes, response compaction.

Modern ICs can have thousands of I/O pins. Large numbers of inputs are

certainly desirable for accessibility of different circuit elements. However, in

terms of vector-based simulations, testing and verification, even a moderate

number of inputs pose a challenge. For example, in order to simulate

exhaustively a simple 32-bit adder, a prohibitive number of 2

patterns need

to be generated. For that reason, subjecting a typical digital circuit to an

exhaustive stimulus during verification is practically impossible.

There are no standard procedures to generate verification vectors - most

techniques are borrowed from manufacturing testing. Test generation

methods can be classified into two categories: random or deterministic.

2.1

Verification Approaches

2.2

Verification by Simulations

2.3

Test Vector Generation

Introduction

Random testing plays a dominant role, and is at the origin of most of the

simulation-based verification methods.

It is impossible to devise an ideal random number generator by

deterministic means; hence all the random techniques are in fact

pseudorandom. This means that vectors are obtained using deterministic

algorithms, where sequences of tests can be always reconstructed, while

appearing to be “random”. Often, stimuli with the uniform distribution

having equal probability of appearance of 0s and 1s are sufficient to provide

high fault coverage. Sometimes it is needed to bias test vectors, such that

the probability of, for example, 1s is larger than that of 0s. Such techniques

are referred to as biased pseudorandom [114] and are widely used in

commercial tools as well as within the open-source SystemC initiative [93].

Another alternative to pseudo-random tests, which recently draw lots of

attention are pseudo-exhaustive methods. As it is infeasible to obtain

pseudo-exhaustive patterns for large number of inputs, k-input spaces are

partitioned into much smaller n-bit subspaces, n << k. This approach rests on

the observation that a k-input circuit under test is often controllable by no

more than n inputs. Hence, test application time is reduced to steps. The

generation of k-bit test vectors that exhaustively exercise all n-bit patterns

has been examined in detail [4], [70], and practical solutions are generally

based on linear feedback shift registers (LFSRs) [87], [124] or cellular

automata [41].

Random techniques do not use extensively information regarding circuit

structure to minimize the test set. The benefit of pseudorandom methods is

definitely the simplicity of test pattern generation. The drawback is the size

of the test set, which can be quite substantial, even for the random testable

circuits.

Deterministic methods like Automated Test Pattern Generation (ATPG)

address the issue of large vector sets. Here, tests are devised to target a

particular fault. Traditionally, these methods were based on the D-algorithm

[110], and are substantially more involved than random methods. They are

essential when the fault list includes redundant faults, i.e., faults that do not

introduce erroneous behavior and cannot be detected by any test patterns.

Note that when an injected fault is redundant, lots of random test vector

simulations could be wasted. Only when subjected to exhaustive testing,

redundant faults are irrelevant. Otherwise, if we use only random patterns,

then we are not able to state with certainty whether undetected faults were

redundant, or test patterns were not able to detect them. In such cases,

deterministic methods are needed to find redundant faults.

Although deterministic methods were traditionally used in manufacturing

testing, recently Al-Assad and Hayes [8] applied them for detecting gate and

wire replacement errors based on the modifications of ATPG. In this work,

剩余225页未读，继续阅读

u011168556

粉丝: 0
资源: 21

误差建模在电子测试前沿的应用

【数据驱动】复杂网络的数据驱动控制附Matlab代码.rar

(源码)基于Qt框架的智能家居管理系统.zip

【路径规划】一种考虑拥塞的改进路径规划算法CCPF-RRT附Matlab代码.rar

基于springboot高性能计算中心的高性能集群共享平台源码数据库文档.zip

(源码)基于JavaFX的图片管理系统.zip

(源码)基于Windows窗体的披萨店厨房管理系统.zip

基于springboot高校创新创业课程体系源码数据库文档.zip

基于springboot汽车美容与保养网站源码数据库文档.zip

基于springboot校友录管理系统源码数据库文档.zip

Cocos2d-x教程视频使用Eclipse在Ubuntu下搭建Cocos2d-x 3集成开发环境

最新资源