Modelsim测试平台：功能验证HDL模型实战

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"Writing Testbench: Functional Verification of HDL Models" 本书是一本专注于Modelsim测试平台编写的权威指南，特别适合于对硬件描述语言（HDL）模型进行功能验证的工程师和专业人士。作者Janick Bergeron是Qualis Design Corporation的专家，他在书中深入探讨了如何有效地构建和使用测试平台来验证数字电路设计。测试平台（Testbench）在电子设计自动化（EDA）领域扮演着至关重要的角色，因为它能确保设计的HDL模型符合预期的行为和性能。在VHDL和Verilog这两种主要的HDL中，编写测试平台是验证设计正确性不可或缺的一部分。书中涵盖了这两个语言的相关内容，尽管书名未明确提及Verilog，但标签表明了该书也涉及这方面的知识。书中内容包括但不限于以下几点： 1. **什么是测试平台？** 作者解释了测试平台的基本概念，它是模拟和验证设计模型的环境，用于提供激励信号并检查设计响应，以确认其正确无误。 2. **测试平台的重要性**：强调了在硬件设计流程中，通过测试平台进行功能验证的必要性，它能够帮助发现和修复潜在的设计错误，从而提高设计的质量和可靠性。 3. **读者应具备的基础知识**：虽然没有详细列出，但根据描述，读者应具备一定的HDL编程基础，特别是VHDL和Verilog，以及基本的数字逻辑和系统设计知识。 4. **阅读路径**：书中可能提供了不同层次的阅读建议，无论是初学者还是有经验的工程师，都能找到适合自己的学习路径。 5. **VHDL与Verilog的对比**：由于这两种语言在测试平台编写中都常用，书中可能会比较它们各自的优缺点，以及在特定情况下的适用性。 6. **更多信息来源**：除了书中的内容，作者可能还提供了其他的学习资源，如网站链接，以便读者进一步扩展知识。 7. **致谢**：作者向对书籍撰写有贡献的人或组织表示感谢，这可能包括同行评审者、合作伙伴和研究团队等。通过这本书，读者将能够学习到创建高效、可靠的测试平台的方法，这对于任何从事数字电路设计验证的人来说都是极其宝贵的资源。书中不仅会讲解理论知识，还可能包含实例和实践技巧，帮助读者将理论应用于实际工程中。

With gate counts and system complexity growing exponentially,

engineers confront the most perplexing challenge in product

design: functional verification. The bulk of the time consumed in

the design of new ICs and systems is now spent on verification.

New and interesting design technologies like physical synthesis and

design reuse that create ever-larger designs only aggravate the

problem. What the EDA tool industry has continuously failed to

realize is that the real problem is not how to create a 12 million gate

IC that runs at 600 MHz, but how to verify it.

The true path to rapid and accurate system verification includes

both tool and methodology innovation. Engineers are compelled to

use the best verification and design tools available to shorten design

cycle time. But it is a grave mistake to assume that simply having

the best tools will result in quality ICs and systems that meet mar-

ket demands and mitigate competitive pressures. Indeed, the best

determinant of successful IC and system design is how the engineer

approaches the problem. The vast majority of engineers still

approach verification using methods dating back a dozen years or

more. If dramatic improvement in verification efficiency is to come

about, real change in the way engineers approach verification is

mandatory and urgent.

A review of available texts on verification reveals a lack of mature

knowledge and leadership on the topic: the EDA tool industry is

conspicuously silent. This text marks the first genuine effort at

Writing Testbenches: Functional Verification of HDL Models

FOREWORD

Preface

Basic language textbooks appeared early in the life of hardware

description languages. They continue to appear as the presentation

styles are refined to facilitate their understanding or as they are

tuned to a particular audience. But the benefits of additional lan-

guage textbooks is quickly diminishing.

Since the introduction of hardware description languages and logic

synthesis technology in the mid 80’s, a lot of expertise on coding

styles and synthesis methodologies has been developed to obtain

desired results. A lot of that expertise has been presented at confer-

ences, has been codified in textbooks, and is available as introduc-

tory and advanced training classes. Early language-focused

textbooks were re-edited to include chapters on synthesizeable cod-

ing and many books entirely devoted to that topic now exist. The

synthesis process, although complex, is now well understood and

many resources are available to communicate that understanding.

Standard procedures and techniques have been developed to pre-

dictably produce adequate results.

At the time I started writing this book, it was going to be the first

book specifically devoted to verification techniques for hardware

models. I will introduce you to the latest verification techniques

that have been successfully used to produce first-time-right ASICs,

Systems-on-a-Chip (SoC), boards, and entire systems.

WHAT THIS BOOK IS ABOUT

I will first introduce the necessary concepts and tools of verifica-

tion, then I’ll describe a process for carrying out an effective func-

tional verification of a design. It is necessary to cover some

language semantics that are often overlooked or oversimplified in

textbooks intent on describing the synthesizeable subset. These

unfamiliar semantics become important in understanding what

makes a well-implemented and robust testbench and in providing

the necessary control and monitor features.

I will also present techniques for applying stimulus and monitoring

the response of a design, by abstracting the operations using bus-

functional models. The architecture of testbenches built around

these bus-functional models is important to minimize development

and maintenance effort.

xviii

Writing Testbenches: Functional Verification of HDL Models

What Prior Knowledge You Should Have

Behavioral modeling is another important concept presented in this

book. It is used to parallelize the implementation and verification of

a design and to perform more efficient simulations. For many,

behavioral modeling is synonymous with synthesizeable or RTL

modeling. In this book, the term “behavioral” is used to describe

any model that adequately emulates the functionality of a design,

usually using non-synthesizeable constructs and coding style.

WHAT PRIOR KNOWLEDGE YOU SHOULD HAVE

This book focuses on the functional verification of hardware

designs using either VHDL or Verilog. I expect the reader to have

at least a basic knowledge of one of the languages. Ideally, you

should have experience in writing synthesizeable models and be

familiar with running a simulation using any of the available

VHDL or Verilog simulators. There will be no description of lan-

guage syntax or grammar. It may be a good idea to have a copy of a

language-focused textbook as a reference along with this book

. I

do not describe the synthesizeable subset, nor limit the implementa-

tion of the verification techniques to using that subset. Verification

is a complex task: the power of either language will be used to their

fullest.

I also expect that you have a basic understanding of digital hard-

ware design. This book uses several hypothetical designs from var-

ious domains of application (video, datacom, computing, etc.).

How these designs are actually specified, architected, then imple-

mented is beyond the scope of this book. The content focuses on the

specification, architecture, then implementation of the verification

of these same designs.

1. For Verilog, I recommend The Verilog Hardware Description Language

by Thomas & Moorby, 3rd edition or later (Kluwer Academic Pub-

lisher). For VHDL, I recommend VHDL Coding Styles and Methodolo-

gies by Ben Cohen (Kluwer Academic Publisher).

Writing Testbenches: Functional Verification of HDL Models

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