AMD64 System V ABI规范：处理器接口与编程模型详解

linux

systemv

需积分: 5 178 浏览量更新于2024-07-09 收藏 491KB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

System V Application Binary Interface (System V ABI) 是一种标准，定义了在Linux系统上不同处理器架构之间共享兼容性的应用程序接口。这个文档针对的是AMD64架构处理器补充版本1.0，涵盖了LP64和ILP32编程模型，发布于2021年6月15日。该文档详细阐述了软件安装、低级系统信息、操作系统接口、函数调用序列以及编码示例等内容。 1. **Introduction**：System V ABI的目标是确保跨不同Linux发行版和处理器平台上的二进制可移植性，让开发者可以编写一次代码，运行在各种环境中。它定义了程序如何与硬件交互，包括处理器架构、数据表示和内存管理等关键细节。 2. **Software Installation**：这部分可能讨论了如何在支持System V ABI的Linux系统上正确安装和配置软件，确保其能在目标平台上正确运行，无论该平台使用哪种处理器。 3. **Low-Level System Information**： - **Machine Interface**：涵盖了处理器的特性，如32位（ILP32）和64位（LP64）模式，以及处理器特有的寄存器和数据结构。 - **Data Representation**：定义了数据类型和内存对齐规则，这对于理解不同架构之间的数据如何在内存中存储至关重要。 - **Function Calling Sequence**：详细描述了函数调用时的参数传递方式，包括使用的寄存器、堆栈布局以及异常处理机制。 4. **Operating System Interface**： - **Exception Interface**：涉及处理器异常处理和错误处理，如信号处理、陷阱和中断。 - **Virtual Address Space**：解释了虚拟地址的使用，包括页大小、地址分配以及内存映射规则。 - **PageSize**：明确指出系统的页面大小，这对于理解和优化内存访问性能是必要的。 - **Virtual Address Assignments**：描述了程序和数据在虚拟地址空间中的分配策略。 5. **Process Initialization**： - **Initial Stack and Register State**：初始化过程中的栈和寄存器设置，这对于程序启动时的行为有直接影响。 - **Thread State**：阐述线程的创建和初始化状态，包括上下文切换和同步机制。 - **Auxiliary Vector**：可能是指辅助数据结构，用于传递附加信息给进程或线程。 6. **Coding Examples**：文档提供了实际的编程示例，展示了如何遵循System V ABI的规定，同时解释了在实现特定功能时遇到的约束和约定。 System V Application Binary Interface 1.0 for AMD64 Architecture Processor Supplement 是一个关键的参考文档，为开发人员提供了一致性和可移植性的指导，确保他们在Linux系统上编写出可以在多种AMD64架构处理器上无缝运行的应用程序。通过理解并遵循这些规定，开发者可以减少兼容性问题，提高代码的效率和可靠性。

资源详情

资源推荐

shared object with the -march=x86-64-v3 GCC ﬂag. The resulting shared object

needs to be installed into the directory /usr/lib64/glibc-hwcaps/x86-64-v3

or /usr/lib/x86_64-linux-gnu/glibc-hwcaps/x86-64-v3 (in case of dis-

tributions with a multi-arch ﬁle system layout). In order to support systems that only

implement the K8 baseline, a fallback implementation must be installed into the default

locations, /usr/lib64 or /usr/lib/x66_64-linux/gnu. It has to be built with

-march=x86-64 (the upstream GCC default). If this guideline is not followed, loading

the library will fail on systems that do not support the level for which the optimized shared

object was built.

Shared objects that are installed under the matching glibc-hwcaps subdirectory

can use the CPU features for this level and earlier levels without further detection logic.

Run-time detection for other CPU features not listed in this section, or listed only under

later levels, is still required (even if all current CPUs implement certain CPU features

together).

If a distribution requires support for a certain level, they build everything with the

appropriate -march= option and install the built binaries in the default ﬁle system loca-

tions. When targeting such distributions, programmers can build their binaries with the

same -march= option and install them into the default locations. Optimized shared ob-

jects for later levels can still be installed into subdirectories with the appropriate name.

3.1.2 Data Representation

Within this speciﬁcation, the term byte refers to a 8-bit object, the term twobyte refers to

a 16-bit object, the term fourbyte refers to a 32-bit object, the term eightbyte refers to a

64-bit object, and the term sixteenbyte refers to a 128-bit object.

Fundamental Types

Figure 3.1 shows the correspondence between ISO C’s scalar types and the processor’s.

__int128, _Float16, __float80, __float128, __m64, __m128, __m256 and __m512 types are

optional.

The __float128 type uses a 15-bit exponent, a 113-bit mantissa (the high order signif-

icant bit is implicit) and an exponent bias of 16383.

The Intel386 ABI uses the term halfword for a 16-bit object, the term word for a 32-bit object, the term

doubleword for a 64-bit object. But most IA-32 processor speciﬁc documentation deﬁne a word as a 16-bit

object, a doubleword as a 32-bit object, a quadword as a 64-bit object and a double quadword as a 128-bit

object.

Initial implementations of the AMD64 architecture are expected to support operations on the

__float128 type only via software emulation.

AMD64 ABI 1.0 – June 15, 2021 – 18:55

Figure 3.1: Scalar Types

Alignment AMD64

Type C sizeof (bytes) Architecture

_Bool

†

1 1 boolean

char 1 1 signed byte

signed char

unsigned char 1 1 unsigned byte

signed short 2 2 signed twobyte

unsigned short 2 2 unsigned twobyte

Integral signed int 4 4 signed fourbyte

enum

†††

unsigned int 4 4 unsigned fourbyte

signed long (LP64) 8 8 signed eightbyte

unsigned long (LP64) 8 8 unsigned eightbyte

signed long (ILP32) 4 4 signed fourbyte

unsigned long (ILP32) 4 4 unsigned fourbyte

signed long long 8 8

††††

signed eightbyte

unsigned long long 8 8

††††

unsigned eightbyte

__int128

††

16 16 signed sixteenbyte

signed __int128

††

16 16 signed sixteenbyte

unsigned __int128

††

16 16 unsigned sixteenbyte

Pointer any-type

(LP64) 8 8 unsigned eightbyte

any-type (

)() (LP64)

any-type

(ILP32) 4 4 unsigned fourbyte

any-type (

)() (ILP32)

_Float16

††††††

2 2 16-bit (IEEE-754)

float 4 4 single (IEEE-754)

Floating- double 8 8

††††

double (IEEE-754)

point __float80

††

16 16 80-bit extended (IEEE-754)

long double

†††††

16 16 80-bit extended (IEEE-754)

__float128

††

16 16 128-bit extended (IEEE-754)

long double

†††††

16 16 128-bit extended (IEEE-754)

Decimal- _Decimal32 4 4 32bit BID (IEEE-754R)

ﬂoating- _Decimal64 8 8 64bit BID (IEEE-754R)

point _Decimal128 16 16 128bit BID (IEEE-754R)

Packed __m64

††

8 8 MMX and 3DNow!

__m128

††

16 16 SSE and SSE-2

__m256

††

32 32 AVX

__m512

††

64 64 AVX-512

†

This type is called bool in C++.

††

These types are optional.

†††

C++ and some implementations of C permit enums larger than an int. The underlying type is bumped

to an unsigned int, long int or unsigned long int, in that order.

††††

The long long, signed long long, unsigned long long and double types have

4-byte alignment in the Intel386 ABI.

†††††

The long double type is 128-bit, the same as the __float128 type, on the Android™

platform. More information on the Android™ platform is available from http://www.android.

com/.

††††††

The _Float16 type, from ISO/IEC TS 18661-3:2015, is optional.

AMD64 ABI 1.0 – June 15, 2021 – 18:55

The long double type uses a 15 bit exponent, a 64-bit mantissa with an explicit high

order signiﬁcant bit and an exponent bias of 16383.

Although a long double requires 16

bytes of storage, only the ﬁrst 10 bytes are signiﬁcant. The remaining six bytes are tail

padding, and the contents of these bytes are undeﬁned.

The __int128 type is stored in little-endian order in memory, i.e., the 64 low-order bits

are stored at a a lower address than the 64 high-order bits.

The value of _Alignof(max_align_t) is 16.

A null pointer (for all types) has the value zero.

The type size_t is deﬁned as unsigned long for LP64 and unsigned int for ILP32.

Booleans, when stored in a memory object, are stored as single byte objects the value

of which is always 0 (false) or 1 (true). When stored in integer registers (except for

passing as arguments), all 8 bytes of the register are signiﬁcant; any nonzero value is

considered true.

Like the Intel386 architecture, the AMD64 architecture in general does not require all

data accesses to be properly aligned. Misaligned data accesses are slower than aligned

accesses but otherwise behave identically. The only exceptions are that __m128, __m256

and __m512 must always be aligned properly.

Aggregates and Unions

Structures and unions assume the alignment of their most strictly aligned component. Each

member is assigned to the lowest available offset with the appropriate alignment. The size

of any object is always a multiple of the object‘s alignment.

An array uses the same alignment as its elements, except that a local or global array

variable of length at least 16 bytes or a C99 variable-length array variable always has

alignment of at least 16 bytes.

Structure and union objects can require padding to meet size and alignment constraints.

The contents of any padding is undeﬁned.

Bit-Fields

C struct and union deﬁnitions may include bit-ﬁelds that deﬁne integral values of a speci-

ﬁed size.

The ABI does not permit bit-ﬁelds having the type __m64, __m128, __m256 or

__m512. Programs using bit-ﬁelds of these types are not portable.

This type is the x87 double extended precision data type.

The alignment requirement allows the use of SSE instructions when operating on the array. The com-

piler cannot in general calculate the size of a variable-length array (VLA), but it is expected that most VLAs

will require at least 16 bytes, so it is logical to mandate that VLAs have at least a 16-byte alignment.

AMD64 ABI 1.0 – June 15, 2021 – 18:55

3.2 Function Calling Sequence

This section describes the standard function calling sequence, including stack frame lay-

out, register usage, parameter passing and so on.

The standard calling sequence requirements apply only to global functions. Local

functions that are not reachable from other compilation units may use different conven-

tions. Nevertheless, it is recommended that all functions use the standard calling sequence

when possible.

3.2.1 Registers

The AMD64 architecture provides 16 general purpose 64-bit registers. In addition the

architecture provides 16 SSE registers, each 128 bits wide and 8 x87 ﬂoating point reg-

isters, each 80 bits wide. Each of the x87 ﬂoating point registers may be referred to in

MMX/3DNow! mode as a 64-bit register. All of these registers are global to all procedures

active for a given thread.

Intel AVX (Advanced Vector Extensions) provides 16 256-bit wide AVX registers

(%ymm0 - %ymm15). The lower 128-bits of %ymm0 - %ymm15 are aliased to the respective 128b-bit

SSE registers (%xmm0 - %xmm15). Intel AVX-512 provides 32 512-bit wide SIMD registers

(%zmm0 - %zmm31). The lower 128-bits of %zmm0 - %zmm31 are aliased to the respective 128b-

bit SSE registers (%xmm0 - %xmm31

). The lower 256-bits of %zmm0 - %zmm31 are aliased to the

respective 256-bit AVX registers (%ymm0 - %ymm31

). For purposes of parameter passing and

function return, %xmmN, %ymmN and %zmmN refer to the same register. Only one of them can

be used at the same time. We use vector register to refer to either SSE, AVX or AVX-512

64-bit wide.

Intel Advanced Matrix Extensions (Intel AMX) is a programming paradigm consisting

of two components: a set of 2-dimensional registers (tiles) representing sub-arrays from a

larger 2-dimensional memory image, and accelerators able to operate on tiles. Capability

of Intel AMX implementation is enumerated by palettes. Two palettes are supported:

palette 0 represents the initialized state and palette 1 consists of 8 tile registers (%tmm0 -

%tmm7) of up to 1 KB size, which is controlled by a tile control register.

This subsection discusses usage of each register. Registers %rbp, %rbx and %r12 through

%r15 “belong” to the calling function and the called function is required to preserve their

values. In other words, a called function must preserve these registers’ values for its

%xmm15 - %xmm31 are only available with Intel AVX-512.

%ymm15 - %ymm31 are only available with Intel AVX-512.

AMD64 ABI 1.0 – June 15, 2021 – 18:55

剩余148页未读，继续阅读

天马行空_xaut

粉丝: 101
资源: 14

AMD64 System V ABI规范：处理器接口与编程模型详解

System V Application Binary Interface pdf

SYSTEM V APPLICATION BINARY INTERFACE

SYSTEM V APPLICATION BINARY INTERFACE Edition 4.1, UNIX ABI pdf

error: vndk library: android.hardware.broadcastradio@2.0's abi has incompati

ERROR:torch.distributed.elastic.multiprocessing.api:failed (exitcode: 1) local_rank: 0 (pid: 27626) of binary:

ERROR:torch.distributed.elastic.multiprocessing.api:failed (exitcode: 1) local_rank: 0 (pid: 4634) of binary:

ReadWrite_c.cpp:(.text+0xce): undefined reference to `_binary_ning_txt_start' /usr/bin/ld: ReadWrite_c.cpp:(.text+0xdc): undefined reference to `_binary_ning_txt_end'

metric.binary.dc((y[:,1,...] > 0.5).cpu().data.numpy(), label_batch[:args.la

ERROR:torch.distributed.elastic.multiprocessing.api:failed (exitcode: 1) local_rank: 0 (pid: 2865) of binary

bash: ./a.out: cannot execute binary file: Exec format error

二叉树的基本操作 内容：使用二叉链表存储结构建立一棵二叉树，完成如下功能： 1.创建二叉树 2.先序遍历二叉树 3.中序遍历二叉树 4.后序遍历二叉树 5.求二叉树深度 6.求二叉树叶子结点个数

ERROR: When restricting platform and interpreter constraints using --python-version, --platform, --abi, or --implementation, either --no-deps must be set, or --only-binary=:all: must be set and --no-binary must not be set (or must be set to :none:).

Expected browser binary location, but unable to find binary in default location, no 'moz:firefoxOptions.binary' capability provided, and no binary flag set on the command line

最新资源

二叉树的基本操作内容：使用二叉链表存储结构建立一棵二叉树，完成如下功能： 1.创建二叉树 2.先序遍历二叉树 3.中序遍历二叉树 4.后序遍历二叉树 5.求二叉树深度 6.求二叉树叶子结点个数